PXN20RM Datasheet, PDF (61/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Introduction
1.7.25 Media Local Bus (MLB)
The following summarizes the MLB configuration:
• Support of 16 logical channels running at a maximum speed of 1024 Fs
• Transmission of commands and data and reception of receive status when functioning as the
transmitting device associated with a logical channel address
• Reception of commands and data and transmission as receive status responses when functioning
as the receiving device associated with a logical channel address
• System channel command handling
• Internal DMA operation
• Local channel buffer RAM (single port RAM) size of 2048  36 bits words
• Support for 3-pin only
• Support for MLB I/O voltage specs 2.5 V (nominal) and 3.3 V (nominal)
NOTE
The MLB is available on the PXN21 only.
1.7.26 Real Time Counter (RTC)
Real Time counter supports wake-up from Low Power modes or real time clock generation
• Configurable resolution for different timeout periods
— 1 sec resolution for > 1 hour period
— 1 ms resolution for 2-second period
• Selectable clock sources from:
— Internal 128 kHz RC oscillator
— Internal 16 MHz RC oscillator
— 32 kHz external oscillator
• RTC supports continued operation through reset, count only reset manually, or by power on reset
(POR)
1.7.27 JTAG Controller (JTAGC)
The JTAGC is compliant with the IEEE 1149.1-2001standard and has the following main features:
• IEEE 1149.1-2001 test access port (TAP) interface
• A JCOMP input that provides the ability to share the TAP
• A 5-bit instruction register that supports several IEEE 1149.1-2001 defined instructions, as well as
several public and private MCU specific instructions
• Three test data registers: Bypass register, boundary scan register and a device identification register
• Supporting boundary scan testing
• TAP controller state machine
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
1-19