PXN20RM Datasheet, PDF (761/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

FlexRay Communication Controller (FlexRAY)
26.6.19.1 System Bus Illegal Address Access
If the system bus detects an controller access to an illegal address, the controller receives a notification
from the system bus about this event and sets the ILSA_EF flag in the CHI Error Flag Register
(CHIERFR).
26.6.19.2 System Bus Access Timeout
The controller starts a timer when it has send an access request to the system bus. This timer expires after
2 * SYMATOR.TIMEOUT + 2 system bus clock cycles. If the access is not finished within this amount
of time, the SBCF_EF flag in the CHI Error Flag Register (CHIERFR) is set.
NOTE
If the system memory read access that retrieves the first message buffer
header data from a FlexRay transmit buffer fails due to a system memory
access timeout or illegal address access, it is possible that the slot status
information for the previous slot is written into the currently used transmit
message buffer. In this case, the slot status information is not written into the
message buffer assigned to the last slot. Thus, both the message buffer
assigned to the last slot, and the currently used transmit message buffer
contain incorrect slot status information. However, if this occurs, either the
System Bus Communication Failure Error Flag (SBCF_EF) or the Illegal
System Bus Address Error Flag (ILSA_EF) will be set in the Controller
Host Interface Error Flag Register (CHIERFR).
The FlexRay module and the system memory subsystem should be
configured to avoid the occurrence of system memory access timeouts and
illegal address accesses. In case that one of the error flags
CHIERFR[SBCF_EF] or CHIERFR[ILSA_EF] is set, the application
should not use the slot status information of the message buffers.
26.6.19.3 Continue after System Bus Failure
If the SBFF bit in the Module Configuration Register (MCR) is 0, the controller will continue its operation
after the occurrence of the system bus access failure but will not generate any system bus accesses until
the start of the next communication cycle.
If a frame is under transmission when the system bus failure occurs, a correct frame is generated with the
remaining header and frame data are replaced by all zeros. Depending on the point in time this can affect
the PPI bit, the Header CRC, the Payload Length in case of an dynamic slot, and the payload data. Starting
from the next slot in the current cycle, no frames will be transmitted and received, except for the key slot,
where a sync or startup null-frame is transmitted, if the key slot is assigned.
If a frame is received when the system bus failure occurs, the reception is aborted and the related receive
message buffer is not updated.
Normal operation is resumed after the start of next communication cycle.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
26-147