PXN20RM Datasheet, PDF (897/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Controller Area Network (FlexCAN)
Table 29-7. CANx_MCR Field Descriptions (continued)
Field
Description
SOFT_RST
Soft Reset. When asserted, FlexCAN resets its internal state machines and some of the memory-mapped
registers. The following registers are affected by soft reset:
• CANx_MCR (except the MDIS bit)
• CANx_TIMER
• CANx_ECR
• CANx_ESR
• CANx_IMASK1
• CANx_IMASK2
• CANx_IFLAG1
• CANx_IFLAG2
Configuration registers that control the interface to the CAN bus are not affected by soft reset. The following
registers are unaffected:
• CANx_CTRL
• CANx_RXGMASK
• CANx_RX14MASK
• CANx_RX15MASK
• All message buffers
The SOFT_RST bit can be asserted directly by the CPU when it writes to the CANx_MCR, but it is also asserted
when global soft reset is requested at MCU level. Because soft reset is synchronous and has to follow a
request/acknowledge procedure across clock domains, it may take some time to fully propagate its effect. The
SOFT_RST bit remains asserted while reset is pending, and is automatically negated when reset completes.
Therefore, software can poll this bit to know when the soft reset has completed.
0 No reset request.
1 Resets values in registers indicated above.
FRZ_ACK
Freeze Mode Acknowledge. Indicates that FlexCAN is in freeze mode and its prescaler is stopped. The freeze
mode request cannot be granted until current transmission and reception processes have finished. Therefore the
software can poll the FRZ_ACK bit to know when FlexCAN has actually entered freeze mode. If freeze mode
request is negated, then this bit is negated once the FlexCAN prescaler is running again. If freeze mode is
requested while FlexCAN is disabled, then the FRZ_ACK bit is only set when the low-power mode is exited. See
Section 29.4.8.1, Freeze Mode, for more information.
0 FlexCAN not in freeze mode, prescaler running.
1 FlexCAN in freeze mode, prescaler stopped.
WRN_EN
Warning Interrupt Enable. When set, this bit enables the generation of the TWRN_INT and RWRN_INT flags in
the error and status register. If WRN_EN is negated, the TWRN_INT and RWRN_INT flags is always 0,
independent of the values of the error counters, and no warning interrupt is ever generated.
1 TWRN_INT and RWRN_INT bits are set when the respective error counter transition from < 96 to  96.
0 TWRN_INT and RWRN_INT bits are 0, independent of the values in the error counters.
LPM_ACK
Low-Power Mode Acknowledge. Indicates whether FlexCAN is disabled. This cannot be performed until all
current transmission and reception processes have finished, so the CPU can poll the LPM_ACK bit to know when
FlexCAN has actually been disabled. See Section 29.4.8.2, Module Disabled Mode, for more information.
0 FlexCAN not disabled.
1 FlexCAN is disabled.
SRX_DIS
Self Reception Disable. This bit defines whether FlexCAN is allowed to receive frames transmitted by itself. If this
bit is set, frames transmitted by the module are not stored in any MB, regardless if the MB is programmed with
an ID that matches the transmitted frame, and no interrupt flag or interrupt signal is generated due to the frame
reception.
0 Self reception enabled.
1 Self reception disabled.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
29-13