PXN20RM Datasheet, PDF (108/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Signal Description
3.4.11.6 Nexus Message Start/End Out
MSEO[1:0]
MSEO[1:0] are outputs that indicate when messages start and end on the MDO pins.
3.4.12 Reset and Configuration Signals
3.4.12.1 External Reset Input
RESET
The RESET pin is a bidirectional I/O pin. It is asserted by an external device to reset the all modules of
the device MCU. It is also an open drain output signal that is asserted during an internal reset. For more
information, see Chapter 4, Resets.
3.4.13 JTAG Signals
For more information, see Chapter 35, IEEE 1149.1 Test Access Port Controller (JTAGC).
3.4.13.1 JTAG Test Clock Input
TCK
TCK provides the clock input for the on-chip test logic.
3.4.13.2 JTAG Test Data Input
TDI
TDI provides the serial test instruction and data input for the on-chip test logic.
3.4.13.3 JTAG Test Data Output
TDO
TDO provides the serial test data output for the on-chip test logic.
3.4.13.4 JTAG Test Mode Select Input
TMS
TMS controls test mode operations for the on-chip test logic.
3.4.13.5 JTAG Compliance Input
JCOMP
The JCOMP pin is used to enable the JTAG TAP controller.
3.4.13.6 Test Mode Enable Input
TEST
The TEST pin is used to place the chip in test mode. It must be tied to V_SS for normal operation.
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PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor