PXN20RM Datasheet, PDF (845/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Enhanced Modular Input/Output Subsystem (eMIOS200)
In GPIO input mode (MODE = 000_0000),the FLAG generation is determined according to EDPOL and
EDSEL bits and the input pin status can be determined by reading the UCIN bit.
In GPIO output mode (MODE = 000_0001), the unified channel is used as a single output port pin and the
value of the EDPOL bit is permanently transferred to the output flip-flop.
28.4.1.1.2 Single Action Input Capture (SAIC) Mode
In SAIC mode (MODE = 000_0010), when a triggering event occurs on the input pin, the value on the
selected time base is captured into register A2. At the same time, the FLAG bit is set to indicate that an
input capture has occurred. Register EMIOS_CADR[n] returns the value of register A2. The channel is
ready to capture events as soon as SAIC mode is entered coming out from GPIO mode. The events are
captured as soon as they occur, thus reading register A always returns the value of the latest captured event.
Subsequent captures are enabled with no need of further reads from EMIOS_CADR[n] register. The
FLAG is set at any time a new event is captured.
The input capture is triggered by a rising, falling or either edges in the input pin, as configured by EDPOL
and EDSEL bits in EMIOS_CCR[n] register.
Figure 28-15 and Figure 28-16 show how the unified channel can be used for input capture.
Edge detect
Edge detect
Edge detect
Input Signal¹
Selected
Counter Bus
0x000500
0x001000
0x001100
0x001250
0x001525
0x0016A0
FLAG
Set Event
A2 (Captured)
Value²
0xxxxxxx
0x001000
Notes: ¹ After input filter
2 _{EMIOS_CADR[n]  A2}
0x001250
0x0016A0
Figure 28-15. Single Action Input Capture with Rising Edge Triggering Example
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
28-23