PXN20RM Datasheet, PDF (1161/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Nexus Development Interface (NDI)
Table 36-6. SRC Packet Encodings
SRC[3:0]
0b0000
0b0001- 0b0111
0b1000
0b1001- 0b1111
e200z6
Reserved
e200z0
Reserved
Client
36.4.1.6 e200z6 and e200z0 Cross Triggering Control
To enable a debug event in one core to cause a debug event in the other core at approximately the same
time, the EVTO signal from the e200z0 Nexus2+ or e200z6 Nexus3+ is connected to the other core’s devt2
input. When enabled in each core’s Nexus1 DBCR0 register, a pulse of the devt2 signal causes a debug
event to occur. In this case, only one external EVTO signal is generated and each core controls whether or
not EVTO causes a debug event to occur.
Interconnection of debug mode control signals are shown in Figure 36-3.
EVTI
e200z6 Core Complex
EVTO
EVTI
e200z0 Core Complex
devt2
devt2
EVTO
NPC
EVTO
Figure 36-3. Debug Mode Control Interconnections
EVTI
Figure 36-4 shows the flow for configuring the e200z0 Nexus2+ to cause an debug request to the e200z6.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
36-11