PXN20RM Datasheet, PDF (911/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Controller Area Network (FlexCAN)
Offset: Base + 0880 - 0x0975
Access: User read/write
0
R
MI31
W
1
MI30
2
MI29
3
MI28
4
MI27
5
MI26
6
MI25
7
MI24
8
MI23
9
MI22
10
MI21
11
MI20
12
MI19
13
MI18
14
MI17
15
MI16
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
MI15 MI14 MI13 MI12 MI11 MI10 MI9 MI8 MI7 MI6 MI5 MI4 MI3 MI2 MI1 MI0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 29-15. Rx Individual Mask Registers (CANx_RXIMR0 – CANx_RXIMR63)
Table 29-16. CANx_RXIMR0 – CANx_RXIMR63 Field Descriptions
Field
Description
MI31–M0
Mask Bits
For normal Rx MBs, the mask bits affect the ID filter programmed on the MB. For the Rx FIFO, the mask bits affect
all bits programmed in the filter table (ID, IDE, RTR).
0 The corresponding bit in the filter is “don’t care.”
1 The corresponding bit in the filter is checked against the one received.
29.4 Functional Description
The FlexCAN module is a CAN protocol engine with a very flexible mailbox system for transmitting and
receiving CAN frames. The mailbox system is composed by a set of as many as 64 message buffers (MB)
that store configuration and control data, time stamp, message ID and data (see Section 29.3.2, Message
Buffer Structure). The memory corresponding to the first eight MBs can be configured to support a FIFO
reception scheme with a powerful ID filtering mechanism, capable of checking incoming frames against
a table of IDs (as many as eight extended IDs or 16 standard IDs or 32 8-bit ID slices), each one with its
own individual mask register. Simultaneous reception through FIFO and mailbox is supported. For
mailbox reception, a matching algorithm makes it possible to store received frames only into MBs that
have the same ID programmed on its ID field. A masking scheme makes it possible to match the ID
programmed on the MB with a range of IDs on received CAN frames. For transmission, an arbitration
algorithm decides the prioritization of MBs to be transmitted based on the message ID (optionally
augmented by 3 local priority bits) or the MB ordering.
Before proceeding with the functional description, an important concept must be explained. A message
buffer is said to be “active” at a given time if it can participate in the matching and arbitration algorithms
that are happening at that time. An Rx MB with a ‘0000’ code is inactive (refer to Table 29-4). Similarly,
a Tx MB with a ‘1000’ or ‘1001’ code is also inactive (refer to Table 29-5). An MB not programmed with
‘0000’, ‘1000’ or ‘1001’ is temporarily deactivated (does not participate in the current arbitration or
matching run) when the CPU writes to the C/S field of that MB (see Section 29.4.5.2, Message Buffer
Deactivation).
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
29-27