PXN20RM Datasheet, PDF (1077/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Cross Triggering Unit (CTU)
Table 33-9. CTU Trigger Sources (continued)
Trigger Number
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Module
eMIOS
eMIOS
eMIOS
eMIOS
eMIOS
eMIOS
eMIOS
eMIOS
eMIOS
eMIOS
eMIOS
eMIOS
eMIOS
eMIOS
eMIOS
eMIOS
eMIOS
eMIOS
eMIOS
eMIOS
eMIOS
eMIOS
eMIOS
PIT
Source
Channel_9
Channel_10
Channel_11
Channel_12
Channel_13
Channel_14
Channel_15
Channel_16
Channel_17
Channel_18
Channel_19
Channel_20
Channel_21
Channel_22
Channel_23
Channel_24
Channel_25
Channel_26
Channel_27
Channel_28
Channel_29
Channel_30
Channel_31
PIT_4
Whenever a flag is set in a particular counter group, the corresponding counter loads the value from one
of the start value registers depending on the delay selection bits. An acknowledgement signal is sent to
eMIOS/PIT to clear the flag. In case more than one flag is set in the same counter group, the lower index
flag is given priority and the corresponding delay value is loaded into the counter.
The acknowledgment signal can be forced to ‘1’ by setting the CLR_FLAG bit of the CTU_EVTCFGRn
register. These bits are implemented for only those input flags to which PIT flags are connected. The
purpose to provide these bits is to have the option of clearing PIT flags by software.
In summary, two levels of arbitration are done before the channel number and trigger are provided to the
ADC:
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
33-9