PXN20RM Datasheet, PDF (388/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

e200z6 Core (Z6)
The cache must be invalidated after a hardware reset; a hardware reset does not invalidate the cache lines.
Following initial power-up, the cache contents are undefined. If the L, D, or V bits are set on any lines, the
software must invalidate cache before the cache is enabled.
Figure 13-15 illustrates the general flow of cache operation.
Physical address
Virtual address
0
19 20
26 27 31
Way 7
Tag data / tag reference
Index
Way 2
Way 1
Way 0
•••
••
••
Set
Select
A[20:26]
Set 0
Set 1
•••
Set 127
Tag
Reference
A[0:19]
Tag
•••
Tag
••
••
Comparator
Status DW0 DW1 DW2 DW3
•••
••• ••• ••• •••
Status DW0 DW1 DW2 DW3
••
MUX
Data or
instruction
7
2
1
HIT 7
• ^• _{HIT 2}
0
HIT 1
HIT 0
Select
Logical OR ^Hit
Figure 13-15. Cache Lookup Flow
To determine if the address is already allocated in the cache the following steps are taken:
1. The cache set index, virtual address bits A[20:26] are used to select one cache set. A set is defined
as the grouping of four or eight lines (one from each way), corresponding to the same index into
the cache array.
2. The higher order physical address bits A[0:19] are used as a tag reference or used to update the
cache line tag field.
3. The four or eight tags from the selected cache set are compared with the tag reference. If any one
of the tags matches the tag reference and the tag status is valid, a cache hit has occurred.
13-24
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor