PXN20RM Datasheet, PDF (1195/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Nexus Development Interface (NDI)
36.6.10.2.4 OTM Flow
Ownership trace messages are generated when the operating system writes to the e200z6 process ID
register or the memory mapped ownership trace register.
The following flow describes the OTM process:
1. The process ID register is a system control register. It is internal to the e200z6 processor and can
be accessed by using PPC instructions mtspr and mfspr. The contents of this register are replicated
on the pins of the processor and connected to Nexus.
2. OTR/process ID register reads do not cause ownership trace messages to be transmitted by the
Nexus3+ module.
3. If the periodic OTM message counter expires (after 255 queued messages without an OTM), an
OTM is sent using the latched data from the previous OTM or process ID register write.
36.6.10.3 Program Trace
This section details the program trace mechanism supported by Nexus3+ for the e200z6 processor.
Program trace is implemented via branch trace messaging (BTM) as per the Class 3 IEEE-ISTO
5001-2003 standard definition. Branch trace messaging for e200z6 processors is accomplished by
snooping the e200z6 virtual address bus (between the CPU and MMU), attribute signals, and CPU status.
36.6.10.3.1 Branch Trace Messaging (BTM)
Traditional branch trace messaging facilitates program trace by providing the following types of
information:
• Messaging for taken direct branches includes how many sequential instructions were executed
since the last taken branch or exception. Direct (or indirect) branches not taken are counted as
sequential instructions.
• Messaging for taken indirect branches and exceptions includes how many sequential instructions
were executed since the last taken branch or exception and the unique portion of the branch target
address or exception vector address.
Branch history messaging facilitates program trace by providing the following information:
• Messaging for taken indirect branches and exceptions includes how many sequential instructions
were executed since the last predicate instruction, taken indirect branch, or exception, the unique
portion of the branch target address or exception vector address, as well as a branch/predicate
instruction history field. Each bit in the history field represents a direct branch or predicated
instruction where a value of one (1) indicates taken, and a value of zero (0) indicates not taken.
Certain instructions (evsel) generate a pair of predicate bits that are both reported as consecutive
bits in the history field.
e200z6 Indirect Branch Message Instructions (Power Architecture Book E)
Table 36-31 shows the types of instructions and events that cause indirect branch messages or branch
history messages to be encoded.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
36-45