PXN20RM Datasheet, PDF (450/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Memory Protection Unit (MPU)
typically reserved for processor cores. The corresponding access control is a 6-bit field defining separate
privilege rights for user and supervisor mode accesses as well as the optional inclusion of a process
identification field within the definition. Bus masters 4–7 are typically reserved for data movement
engines and their capabilities are limited to separate read and write permissions. For these fields, the bus
master number refers to the logical master number defined as the AHB hmaster[3:0]signal.
For the processor privilege rights, there are three flags associated with this function: {read, write, execute}.
In this context, these flags follow the traditional definition:
• Read (r) permission refers to the ability to access the referenced memory address using an operand
(data) fetch.
• Write (w) permission refers to the ability to update the referenced memory address using a store
(data) instruction.
• Execute (x) permission refers to the ability to read the referenced memory address using an
instruction fetch.
The evaluation logic defines the processor access type based on multiple AHB signals: read or write as
specified by the hwrite signal and the low-order two bits of hprot[1:0], which identify a data reference
versus an instruction fetch and the operating mode (supervisor, user) of the requesting processor.
For non-processor data movement engines (bus masters 4–7), the evaluation logic simply uses hwrite to
determine if the access is a read or write. The hprot[1:0] signal is ignored for these masters.
Writes to this word clear the region descriptor’s valid bit. Because it is also expected that system software
may adjust only the access controls within a region descriptor (MPU_RGDn.Word2) as different tasks
execute, an alternate programming view of this 32-bit entity is provided. If only the access controls are
being updated, this operation should be performed by writing to MPU_RGDAACn (alternate access
control n) as stores to these locations do not affect the descriptor’s valid bit.
Offset: MPU_BASE + 0x400 + (16*n) + 0x8 (MPU_RGDn.Word2)
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11 12 13
14
15
R0
W
0
0
M6RE M6WE M5RE M5WE M4RE M4WE
0
0
0
0
0
M2PE
M2S
M
Reset –
–
–
–
–
–
–
–
–
–
– ––– –
–
16
17
18
19
20
21
22
R _M2S
WM
M2UM
r
w
x
M1PE
M1SM
23
24
25
26
27 28 29
M1UM
M0PE M0SM
r
wx
r
Reset –
–
–
–
–
–
–
–
–
–
– –––
Note: Refer to Figure 18-1 to see the Master ID assignments.
Figure 18-8. MPU Region Descriptor, Word 2 Register (MPU_RGDn.Word2)
30
31
M0UM
w
x
–
–
Table 18-8. MPU_RGDn.Word2 Field Descriptions
Field
Description
M6RE Bus Master ID 6 Read Enable. If set, this flag allows bus master ID 6 (FlexRay) to perform read operations. If cleared,
any attempted read by bus master ID 6 terminates with an access error and the read is not performed.
18-10
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor