PXN20RM Datasheet, PDF (625/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Offset
0x0098
0x009A
0x009C
0x009E
0x00A0
...
0x00DC
0x00DE
...
0x00E6
0x00E8
0x00EA
0x00EC
0x00EE
0x00F0
...
0x00FE
0x0100
0x0102
0x0104
0x0106
...
0x04F8
0x04FA
0x04FC
0x04FE
FlexRay Communication Controller (FlexRAY)
Table 26-3. FlexRay Memory Map (continued)
Register
Receive FIFO Range Filter Configuration Register (RFRFCFR)
Receive FIFO Range Filter Control Register (RFRFCTR)
Dynamic Segment Status
Last Dynamic Transmit Slot Channel A Register (LDTXSLAR)
Last Dynamic Transmit Slot Channel B Register (LDTXSLBR)
Protocol Configuration
Protocol Configuration Register 0 (PCR0)
...
Protocol Configuration Register 30 (PCR30)
Access
R/W
R/W
R
R
R/W
–
R/W
Reserved
R
Receive FIFO—Configuration (continued)
Receive FIFO System Memory Base Address High Register (RFSYMBADHR)
R/W
Receive FIFO System Memory Base Address Low Register (RFSYMBADLR)
R/W
Receive FIFO Periodic Timer Register (RFPTR)
R/W
Receive FIFO—Control (continued)
Receive FIFO Fill Level and POP Count Register (RFFLPCR)
R/W
Reserved
R
Message Buffers Configuration, Control, Status
Message Buffer Configuration, Control, Status Register 0 (MBCCSR0)
R/W
Message Buffer Cycle Counter Filter Register 0 (MBCCFR0)
R/W
Message Buffer Frame ID Register 0 (MBFIDR0)
R/W
Message Buffer Index Register 0 (MBIDXR0)
R/W
...
...
Message Buffer Configuration, Control, Status Register 127 (MBCCSR127)
R/W
Message Buffer Cycle Counter Filter Register 127 (MBCCFR127)
R/W
Message Buffer Frame ID Register 127 (MBFIDR127)
R/W
Message Buffer Index Register 127 (MBIDXR127)
R/W
26.5.2 Register Descriptions
This section provides detailed descriptions of all registers in ascending address order, presented as 16-bit
wide entities
Table 26-4 provides a key for the register figures and register tables.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
26-11