PXN20RM Datasheet, PDF (1200/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Nexus Development Interface (NDI)
:
3
2
1
ECODE (00001 / 00111 / 01000)
SRC
TCODE (001000)
MSB
5 bits
4 bits
Fixed length = 15 bits
Figure 36-33. Error Message Format
6 bits LSB
Program Trace Synchronization Messages
A program trace direct/indirect branch with sync message is messaged via the auxiliary port (provided
program trace is enabled) for the following conditions (see Table 36-34):
• Initial program trace message upon the first direct/indirect branch after exit from system reset or
whenever program trace is enabled
• Upon direct/indirect branch after returning from a CPU low power state
• Upon direct/indirect branch after returning from debug mode
• Upon direct/indirect branch after occurrence of queue overrun (can be caused by any trace
message), provided program trace is enabled
• Upon direct/indirect branch after the periodic program trace counter has expired indicating 255
without-sync program trace messages have occurred since the last with-sync message occurred
• Upon direct/indirect branch after assertion of the event in (EVTI) pin if the EIC bits within the DC1
register have enabled this feature
• Upon direct/indirect branch after the sequential instruction counter has expired indicating 255
instructions have occurred between branches
• Upon direct/indirect branch after a BTM message was lost due to an attempted access to a secure
memory location.
• Upon direct/indirect branch after a BTM message was lost due to a collision entering the FIFO
between the BTM message and either a watchpoint message or an ownership trace message
• Upon the first direct/indirect branch message after an execution mode switch
If the Nexus3+ module is enabled at reset, a EVTI assertion initiates a program trace direct/indirect branch
with sync message (if program trace is enabled) upon the first direct/indirect branch. The format for
program trace direct/indirect branch with sync messages is as follows:
4
3
2
1
F-ADDR
I-CNT
SRC
TCODE (001011 or 001100)
MSB 1–32 bits
1–8 bits
4 bits
6 bits
LSB
Max length = 50 bits; Min length = 12 bits
Figure 36-34. Direct/Indirect Branch with Sync Message Format
The formats for program trace direct/indirect branch with sync. messages and indirect branch history with
sync. messages are as follows
36-50
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor