PXN20RM Datasheet, PDF (224/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

System Integration Unit (SIU)
Offset: SIU_BASE + 0x09AC
Access: User read-only
1
1
1
1
1
1
0
1
2
3
4
5
6
1
7
8
9
10
11
12
13
14
15
R
HLT HLT
HLT HLT HLT HLT HLT HLT HLT
0
0
0
0
0
0 ACK ACK 0 ACK ACK ACK ACK ACK ACK ACK
6
7
9 10 11 12 13 14 15
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
16
17
18
19
20
21
22
23
24
R HLT HLT HLT HLT HLT HLT HLT HLT
ACK CK ACK ACK ACK ACK ACK ACK 0
16 17 18 19 20 21 22 23
1
1
25
26
27
28
29 30
31
HLT HLT HLT HLT
HLT
0 ACK ACK ACK ACK 0 ACK
26 27 28 29
31
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1 _{Setting the corresponding bit in SIU_HLT0 sets this bit, but has no other effect.}
Figure 8-28. Halt Acknowledge Register 0 (SIU_HLTACK0)
Table 8-29. SIU_HLTACK0 Register Field Descriptions
Field
Description
HLTACK6
HLTACK7
HLTACK9
HLTACK10
HLTACK11
HLTACK12
HLTACK13
HLTACK14
HLTACK15
HLTACK16
HLTACK17
HLTACK18
HLTACK19
HLTACK20
HLTACK21
HLTACK22
HLTACK23
HLTACK26
HLTACK27
HLTACK28
Halt acknowledge bit 6. When this bit is set, the EMIOS200 module is halted.
Halt acknowledge bit 7. When this bit is set, the PIT module is halted.
Halt acknowledge bit 9. When this bit is set, the CTU module is halted.
Halt acknowledge bit 10. When this bit is set, the FLEXCAN_F module is halted.
Halt acknowledge bit 11. When this bit is set, the FLEXCAN_E module is halted.
Halt acknowledge bit 12. When this bit is set, the FLEXCAN_D module is halted.
Halt acknowledge bit 13. When this bit is set, the FLEXCAN_C module is halted.
Halt acknowledge bit 14. When this bit is set, the FLEXCAN_B module is halted.
Halt acknowledge bit 15. When this bit is set, the FLEXCAN_A module is halted.
Halt acknowledge bit 16. When this bit is set, the ESCI_H module is halted.
Halt acknowledge bit 17. When this bit is set, the ESCI_G module is halted.
Halt acknowledge bit 18. When this bit is set, the ESCI_F module is halted.
Halt acknowledge bit 19. When this bit is set, the ESCI_E module is halted.
Halt acknowledge bit 20. When this bit is set, the ESCI_D module is halted.
Halt acknowledge bit 21. When this bit is set, the ESCI_C module is halted.
Halt acknowledge bit 22. When this bit is set, the ESCI_B module is halted.
Halt acknowledge bit 23. When this bit is set, the ESCI_A module is halted.
Halt acknowledge bit 26. When this bit is set, the DSPI_B module is halted.
Halt acknowledge bit 27. When this bit is set, the DSPI_A module is halted.
Halt acknowledge bit 28. When this bit is set, the I²C_B module is halted.
8-42
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor