PXN20RM Datasheet, PDF (395/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

e200z6 Core (Z6)
Table 13-12. Interrupts and Conditions (continued)
Interrupt
Interrupt Type Vector Offset
Register
Enables¹
Core Register
in Which
State
Information is
Saved
Causing Conditions
Debug
IVOR 15
DE, IDM
CSSR[0:1]
Debugger when HIDO[DAPUEN] = 0. Caused by trap,
instruction address compare, data address compare,
instruction complete, branch taken, return from interrupt,
interrupt taken, debug counter, external debug event,
unconditional debug event
DE, IDM
DSRR[0:1] Debugger when HIDO[DAPUEN] = 1, and caused by same
conditions as above.
Reserved
IVOR 16–31
SPE
IVOR 32
—
SRR[0:1] SPE APU instruction when MSR[SPE] = 0, and see Section
unavailable
exception
5.6.18, SPE APU Unavailable Interrupt, in the e200z6
PowerPC^TM Core Reference Manual, Rev 0.
SPE data
exception
IVOR 33
—
SRR[0:1] SPE FP data exception and see Section 5.6.19, SPE
Floating-Point Data Interrupt, in the e200z6 PowerPC^TM Core
Reference Manual, Rev 0.
SPE round
IVOR 34
—
SRR[0:1] Inexact result from floating-point instruction. See Section
exception
5.6.2, SPE Floating-Point Round Interrupt, in the e200z6
PowerPC^TM Core Reference Manual, Rev 0.
1 _{CE, ME, EE, DE are in the MSR. DIE, FIE, and WIE are in the TCR. “src” signifies the individual enable for each INTC source.}
The debug interrupt, IVOR 15, also requires EDM = 0 (EDM and IDM are in the DBCR0 register).
2 _{Autovectored External and Critical Input interrupts use this IVOR. Vectored interrupts supply an interrupt vector offset}
directly.
13.3.4 Bus Interface Unit (BIU)
The BIU encompasses control and data signals supporting instruction and data transfers. A data bus width
of 64 bits is implemented. The memory interface supports read and write transfers of 8, 16, 24, 32, and 64
bits, supports burst transfers of four doublewords, and operates in a pipelined fashion.
Single-beat transfers are supported for cache-inhibited read and write cycles, and write-buffer writes. Burst
transfers of four doublewords are supported for cache linefill and copyback operations.
13.3.5 Timer Facilities
The core provides a set of registers to provide fixed interval timing and watchdog functions for the system.
All of these must be initialized during start-up. The registers associated with fixed interval timer and
watchdog functions are the following:
• Timer control register (TCR)—provides control of the timer and watchdog facilities.
• Timer status register (TSR)—provides status of the timer facilities.
• Time base registers (TBU and TBL)—two 32-bit registers (upper and lower) that are concatenated
to provide a long-period, 64-bit counter.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
13-31