PXN20RM Datasheet, PDF (606/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Fast Ethernet Controller (FEC)
Table 25-34. Destination Address to 6-Bit Hash (continued)
48-bit DA
7D:ff:ff:ff:ff:ff
FD:ff:ff:ff:ff:ff
DD:ff:ff:ff:ff:ff
9D:ff:ff:ff:ff:ff
BD:ff:ff:ff:ff:ff
6-bit Hash (in
hex)
0x3B
0x3C
0x3D
0x3E
0x3F
Hash Decimal
Value
59
60
61
62
63
25.4.10 Full Duplex Flow Control
Full-duplex flow control allows the user to transmit pause frames and to detect received pause frames.
Upon detection of a pause frame, MAC data frame transmission stops for a given pause duration.
To enable pause frame detection, the FEC must operate in full-duplex mode (TCR[FDEN] asserted) and
flow control enable (RCR[FCE]) must be asserted. The FEC detects a pause frame when the fields of the
incoming frame match the pause frame specifications, as shown in the table below. In addition, the receive
status associated with the frame should indicate that the frame is valid.
Table 25-35. PAUSE Frame Field Specification
48-bit Destination Address
48-bit Source Address
16-bit TYPE
16-bit OPCODE
16-bit PAUSE_DUR
0x0180_C200_0001 or Physical Address
Any
0x8808
0x0001
0x0000 to 0xFFFF
Pause frame detection is performed by the receiver and microcontroller modules. The microcontroller runs
an address recognition subroutine to detect the specified pause frame destination address, while the
receiver detects the TYPE and OPCODE pause frame fields. On detection of a pause frame, TCR[GTS] is
asserted by the FEC internally. When transmission has paused, the EIR[GRA] interrupt is asserted and the
pause timer begins to increment. Note that the pause timer makes use of the transmit backoff timer
hardware, which is used for tracking the appropriate collision backoff time in half-duplex mode. The pause
timer increments once every slot time, until OPD[PAUSE_DUR] slot times have expired. On
OPD[PAUSE_DUR] expiration, TCR[GTS] is deasserted allowing MAC data frame transmission to
resume. Note that the receive flow control pause (TCR[RFC_PAUSE]) status bit is asserted while the
transmitter is paused due to reception of a pause frame.
To transmit a pause frame, the FEC must operate in full-duplex mode and the user must assert flow control
pause (TCR[TFC_PAUSE]). On assertion of transmit flow control pause (TCR[TFC_PAUSE]), the
transmitter asserts TCR[GTS] internally. When the transmission of data frames stops, the EIR[GRA]
(graceful stop complete) interrupt asserts. Following EIR[GRA] assertion, the pause frame is transmitted.
On completion of pause frame transmission, flow control pause (TCR[TFC_PAUSE]) and TCR[GTS] are
deasserted internally.
25-40
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor