PXN20RM Datasheet, PDF (512/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

DMA Channel Multiplexer (DMA_MUX)
Table 23-4. DMA Source Configuration (continued)
DMA Request
DMA_MUX
Source Input
Number
DMA Source
Description
Always enabled
0x3E
Always enabled
Always enabled
Always enabled
0x3F
Always enabled
Always enabled
1 _{Configuring a DMA channel to select source 0 or any of the reserved sources will disable that DMA channel.}
23.4 Functional Description
The primary purpose of the DMA_MUX is to provide flexibility in the system’s use of the available DMA
channels. As such, configuration of the DMA_MUX is intended to be a static procedure done during
execution of the system boot code. However, if the procedure outlined in Section 23.5.2, Enabling and
Configuring Sources, is followed, the configuration of the DMA_MUX may be changed during the normal
operation of the system.
Functionally, the DMA_MUX channels may be divided into two classes: channels 0–7, which implement
the normal routing functionality and periodic triggering capability, and channels 8–31, which implement
only the normal routing functionality.
23.4.1 DMA Channels 0–7
In addition to the normal routing functionality, channels 0–7 of the DMA_MUX provide a special periodic
triggering capability that can be used to provide an automatic mechanism to transmit bytes, frames, or
packets at fixed intervals without the need for processor intervention. The trigger is generated by the
periodic interrupt timer (PIT); as such, the configuration of the periodic triggering interval is done via
configuration registers in the PIT. Please refer to the periodic interrupt timer block guide for more
information on this topic.
NOTE
Because of the dynamic nature of the system (i.e.,DMA channel priorities,
bus arbitration, interrupt service routine lengths, etc.), the number of clock
cycles between a trigger and the actual DMA transfer cannot be guaranteed.
23-8
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor