PXN20RM Datasheet, PDF (225/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

System Integration Unit (SIU)
Table 8-29. SIU_HLTACK0 Register Field Descriptions (continued)
Field
HLTACK29
HLTACK31
Description
Halt acknowledge bit 29. When this bit is set, the I²C_A module is halted.
Halt acknowledge bit 31. When this bit is set, the ADC module is halted.
Offset: SIU_HLTACK1: SIU_BASE + 0x09B0
Access: User read-only
1
1
1
1
1
1
1
1
1
1
1
1
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R HLT HLT
HLT HLT
ACK ACK 0 ACK ACK 0
0
0
0
0
0
0
0
0
0
0
0
1
3
4
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
16
17
18
19
20
21
22
23
24
25
26
27
28
29 30
31
R
HLT HLT HLT HLT
HLT HLT HLT HLT
0
0
0
0 ACK ACK ACK ACK 0 0 ACK ACK ACK ACK 0 0
20 21 22 23
26 27 28 29
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1 _{Setting the corresponding bit in SIU_HLT0 sets this bit, but has no other effect.}
Figure 8-29. Halt Acknowledge Register 1 (SIU_HLTACK1)
Table 8-30. SIU_HLTACK1 Register Field Descriptions
Field
Description
HLTACK0
HLTACK1
HLTACK3
HLTACK4
HLTACK20
HLTACK21
HLTACK22
HLTACK23
HLTACK26
HLTACK27
HLTACK28
HLTACK29
Halt acknowledge bit 0. When this bit is set, the Z6 core is halted.
Note: This flag indicates a core-generated halt, not a halt caused by writing to SIU_HLT10[HLT0].
Halt acknowledge bit 1. When this bit is set, the Z0 core is halted.
Note: This flag indicates a core-generated halt, not a halt caused by writing to SIU_HLT1[HLT1].
Halt acknowledge bit 3. When this bit is set, the DMA module is halted.
Halt acknowledge bit 4. When this bit is set, the NPC module is halted.
Halt acknowledge bit 20. When this bit is set, the ESCI_M module is halted.
Halt acknowledge bit 21. When this bit is set, the ESCI_L module is halted.
Halt acknowledge bit 22. When this bit is set, the ESCI_K module is halted.
Halt acknowledge bit 23. When this bit is set, the ESCI_J module is halted.
Halt acknowledge bit 26. When this bit is set, the DSPI_D module is halted.
Halt acknowledge bit 27. When this bit is set, the DSPI_C module is halted.
Halt acknowledge bit 28. When this bit is set, the I²C_D module is halted.
Halt acknowledge bit 29. When this bit is set, the I²C_C module is halted.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
8-43