PXN20RM Datasheet, PDF (922/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Controller Area Network (FlexCAN)
Table 29-18. CAN Standard Compliant Bit Time Segment Settings (continued)
Time Segment 1
8 .. 15
9 .. 16
Time Segment 2
7
8
Resynchronization
Jump Width
1 .. 4
1 .. 4
29.4.7.5 Arbitration and Matching Timing
During normal transmission or reception of frames, the arbitration, match, move in and move out processes
are executed during certain time windows inside the CAN frame, as shown in Figure 29-17. When doing
matching and arbitration, FlexCAN needs to scan the whole message buffer memory during the available
time slot. In order to have sufficient time to do that, the following restrictions must be observed:
• A valid CAN bit timing must be programmed, as indicated in Figure 29-17.
• The system clock frequency cannot be smaller than the oscillator clock frequency, i.e.,the PLL
cannot be programmed to divide down the oscillator clock.
• There must be a minimum ratio of 16 between the system clock frequency and the CAN bit rate.
CRC (15)
Start Move
(bit 6)
EOF (7)
Intermi¹
Matching/Arbitration Window (24 bits)
Move
Window
1 _{Intermi = Intermission}
Figure 29-17. Arbitration, Match and Move Time Windows
29.4.8 Modes of Operation Details
29.4.8.1 Freeze Mode
This mode is entered by asserting the HALT bit in the CANx_MCR or when the MCU is put into debug
mode. In both cases it is also necessary that the FRZ bit is asserted in the CANx_MCR. When freeze mode
is requested during transmission or reception, FlexCAN does the following:
• Waits to be in either intermission, passive error, bus off or idle state
• Waits for all internal activities like move in or move out to finish
• Ignores the Rx input pin and drives the Tx pin as recessive
• Stops the prescaler, thus halting all CAN protocol activities
• Grants write access to the CANx_ECR, which is read-only in other modes
• Sets the NOT_RDY and FRZ_ACK bits in CANx_MCR
29-38
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor