PXN20RM Datasheet, PDF (578/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Fast Ethernet Controller (FEC)
Table 25-4. EIR Field Descriptions (continued)
Field
LC
RL
UN
Description
Late collision. This bit indicates that a collision occurred beyond the collision window (slot time) in half duplex
mode. The frame is truncated with a bad CRC and the remainder of the frame is discarded.
Collision retry limit. This bit indicates that a collision occurred on each of 16 successive attempts to transmit
the frame. The frame is discarded without being transmitted, and transmission of the next frame begins. Can
only occur in half duplex mode.
Transmit FIFO underrun. This bit indicates that the transmit FIFO became empty before the complete frame
was transmitted. A bad CRC is appended to the frame fragment and the remainder of the frame is discarded.
25.3.4.3 Ethernet Interrupt Mask Register (EIMR)
The EIMR register controls which interrupt events are allowed to generate actual interrupts. All
implemented bits in this CSR are read/write. This register is cleared on a hardware reset. If the
corresponding bits in both the EIR and EIMR registers are set, the interrupt is signalled to the CPU. The
interrupt signal remains asserted until a 1 is written to the EIR bit (write 1 to clear) or a 0 is written to the
EIMR bit.
Offset: FEC_BASE + 0x0008
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
HB
ERR
BABR BABT
GRA
TXF
TXB
RXF
RXB
MII
EB
ERR
LC
RL
UN
0
0
0
W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 25-3. Interrupt Mask Register (EIMR)
Table 25-5. EIMR Field Descriptions
Field
Description
See Figure 25-2
and Table 25-4
Interrupt mask. Each bit corresponds to an interrupt source defined by the EIR register. The corresponding
EIMR bit determines whether an interrupt condition can generate an interrupt.
0 The corresponding interrupt source is masked.
1 The corresponding interrupt source is not masked.
Write 1 to clear.
25.3.4.4 Receive Descriptor Active Register (RDAR)
RDAR is a command register, written by the user, that indicates that the receive descriptor ring has been
updated (empty receive buffers have been produced by the driver with the empty bit set).
Whenever the register is written, the R_DES_ACTIVE bit is set. This is independent of the data actually
written by the user. When set, the FEC polls the receive descriptor ring and processes receive frames
25-12
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor