PXN20RM Datasheet, PDF (472/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Error Correction Status Module (ECSM)
Offset: ECSM_BASE_ADDR + 0x0058
Access: User read-only
0
R
W
Reset U
1
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PFEDR[0:15]
U
U
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U
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U
UU U
U
U
U
U
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Reset U
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PFEDR[16:31]
U
U
U
U
U
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UU U
U
U
U
U
Figure 19-8. Platform Flash ECC Data High (PFEDRH) Register
Offset: ECSM_BASE_ADDR + 0x005C
Access: User read-only
0
R
W
Reset U
1
2
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PFEDR[32:47]
U
U
U
U
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UU U
U
U
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U
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Reset U
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PFEDR[48:63]
U
U
U
U
U
U
U
U
UU U
U
U
U
U
Figure 19-9. Platform Flash ECC Data Low (PFEDRL) Register
Table 19-10. PFEDR Field Descriptions
Field
Description
PFEDR Platform Flash ECC Data Register. Contains the data associated with the faulting access of the last properly
enabled platform flash ECC event. The register contains the data value taken directly from the platform data bus.
19.2.2.9 Platform RAM ECC Address Register (PREAR)
The PREAR is a 32-bit register for capturing the address of the last properly enabled ECC event in the
platform RAM memory. Depending on the state of the ECC configuration register, an ECC event in the
platform RAM causes the address, attributes and data associated with the access to be loaded into the
PREAR, PRESR, PREMR, PREAT, and PREDR registers and also the appropriate flag (PR1BC or
PRNCE) in the ECC status register to be asserted.
This register is read-only; any attempted write is ignored. See Figure 19-10 and Table 19-11 for the
PREAR definition.
19-12
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor