PXN20RM Datasheet, PDF (856/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Enhanced Modular Input/Output Subsystem (eMIOS200)
MODE = 000_1011
EMIOS_CCNTR[n]
A1 B1 write _{A1 Match B1 Match}
amount of events detected
amount of events detected
A1 Match B1 Match
0x000000
Flag Pin/Register
Selected Counter Bus
0x000090
A1 Value¹
B1 Value²
A2 Value³
0x000090 0x000090
0x000303
0x000303
0x000090
0x000090
0x000303
A2  EMIOS_CCNTR[n]
Time
0x000303
0x000303
A2  EMIOS_CCNTR[n]
Notes: 1. EMIOS_CADR[n] = A1
2. EMIOS_CBDR[n] = B1
3. EMIOS_ALTA[n] = A2
Figure 28-30. Pulse/Edge Counting Single-Shot Mode Example
28.4.1.1.9 Quadrature Decode (QDEC) Mode
Quadrature decode mode uses UC[n] operating in QDEC mode and the input programmable filter (IPF)
from UC[n – 1]. Note that UC[n – 1] can be configured, at the same time, to an operation mode that does
not use I/O pins, such as MC mode (modulus counter). The connection among the UCs is circular, i.e.,
when UC[0] is running in QDEC mode, the input programmable filter from UC[23] is being used.
This mode generates a FLAG every time the internal counter matches A1 register. The internal counter is
automatically selected and is not cleared when entering this mode.
MODE[0] bit selects which type of encoder is used: count & direction encoder or phase_A & phase_B
encoder.
When operating with count & direction encoder (MODE[6] cleared), UC[n] input pin must be connected
to the direction signal and UC[n – 1] input pin must be connected to the count signal of the quadrature
encoder. UC[n] EDPOL bit selects count direction according to direction signal and UC[n – 1] EDPOL bit
selects if the internal counter is clocked by the rising or falling edge of the count signal.
When operating with phase_A & phase_B encoder (MODE[6] set), UC[n] input pin must be connected to
the phase_A signal and UC[n – 1] input pin must be connected to the phase_B signal of the quadrature
encoder. EDPOL bit selects the count direction according to the phase difference between phase_A &
phase_B signals.
Figure 28-31 and Figure 28-32 show two Unified Channels configured to quadrature decode mode for
count & direction encoder and phase_A & phase_B encoders, respectively.
28-34
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor