PXN20RM Datasheet, PDF (169/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Frequency Modulated Phase-Locked Loop (FMPLL)
Table 7-5. Pre-divider Ratios
EPREDIV
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010–1111
Input Divide Ratio (EPREDIV+1)
1 (default for PXN20)
2
3
4
5
6
Invalid
8
Invalid
10
Invalid
Table 7-6. Feedback Divide Ratios
EMFD
0000_0000–0001_1111
0010_0000
0010_0001
0010_0010
0010_0011
0010_0100
0010_0101
.
.
0011_0000
.
.
1000_0100
1000_0101–1111_1111
Feedback Divide Ratio (EMFD+16)
Invalid
48
49
50
51
52
53
.
.
64 (default for PXN20)
.
.
148
Invalid
7.3.2.3 FMPLL Enhanced Synthesizer Control Register 2 (ESYNCR2)
This is the second of two enhanced versions of the FMPLL synthesizer control register used to access
enhanced features in the FMPLL. The bit fields in the ESYNCR2 behave as described in Figure 7-4.
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
7-7