PXN20RM Datasheet, PDF (609/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

25.4.14.2 Reception Errors
Fast Ethernet Controller (FEC)
25.4.14.2.1 Overrun Error
If the receive block has data to put into the receive FIFO and the receive FIFO is full, the FEC sets the OV
bit in the RxBD. All subsequent data in the frame is discarded. Subsequent frames may also be discarded
until the receive FIFO is serviced by the DMA and space is made available. At this point the receive
frame/status word is written into the FIFO with the OV bit set. This frame must be discarded by the driver.
25.4.14.2.2 Non-Octet Error (Dribbling Bits)
The Ethernet controller handles as many as 7 dribbling bits when the receive frame terminates past an
non-octet aligned boundary. Dribbling bits are not used in the CRC calculation. If there is a CRC error,
then the frame non-octet aligned (NO) error is reported in the RxBD. If there is no CRC error, then no error
is reported.
25.4.14.2.3 CRC Error
When a CRC error occurs with no dribble bits, the FEC closes the buffer and sets the CR bit in the RxBD.
CRC checking cannot be disabled, but the CRC error can be ignored if checking is not required.
25.4.14.2.4 Frame Length Violation
When the receive frame length exceeds MAX_FL bytes, the BABR interrupt is generated, and the LG bit
in the end of frame RxBD is set. The frame is not truncated unless the frame length exceeds 2047 bytes).
25.4.14.2.5 Truncation
When the receive frame length exceeds 2047 bytes the frame is truncated, and the TR bit is set in the
RxBD.
25.5 Buffer Descriptors
This section provides a description of the operation of the driver/DMA via the buffer descriptors. It is
followed by a detailed description of the receive and transmit descriptor fields.
25.5.1 Driver/DMA Operation with Buffer Descriptors
The data for the FEC frames must reside in memory external to the FEC. The data for a frame is placed in
one or more buffers. Associated with each buffer is a buffer descriptor (BD) which contains a starting
address (pointer), data length, and status/control information (which contains the current state for the
buffer). To permit maximum user flexibility, the BDs are also located in external memory and are read in
by the FEC DMA engine.
Software “produces” buffers by allocating/initializing memory and initializing buffer descriptors. Setting
the RxBD[E] or TxBD[R] bit “produces” the buffer. Software writing to either the TDAR or RDAR tells
the FEC that a buffer has been placed in external memory for the transmit or receive data traffic,
respectively. The hardware reads the BDs and “consumes” the buffers after they have been produced. After
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PXN20 Microcontroller Reference Manual, Rev. 1
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