PXN20RM Datasheet, PDF (909/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Controller Area Network (FlexCAN)
Offset: Base + 0x002C
Access: User read/write
0
R _BUF
W ^63I
Reset 0
1
BUF
62I
0
2
BUF
61I
0
3
BUF
60I
0
4
BUF
59I
0
5
BUF
58I
0
6
BUF
57I
0
7
BUF
56I
0
8
BUF
55I
0
9
BUF
54I
0
10
BUF
53I
0
11
BUF
52I
0
12
BUF
51I
0
13
BUF
50I
0
14
BUF
49I
0
15
BUF
48I
0
16
R _BUF
W ^47I
Reset 0
17
BUF
46I
0
18
BUF
45I
0
19
BUF
44I
0
20
BUF
43I
0
21
BUF
42I
0
22
BUF
41I
0
23
BUF
40I
0
24
BUF
39I
0
25
BUF
38I
0
26
BUF
37I
0
27
BUF
36I
0
28
BUF
35I
0
29
BUF
34I
0
30
BUF
33I
0
31
BUF
32I
0
Figure 29-13. Interrupt Flag 2 Register (CANx_IFLAG2)
Table 29-14. CANx_IFLAG2 Field Descriptions
Field
BUFnI
Description
Message Buffer n Interrupt. Each bit represents the respective FlexCAN message buffer (MB63–MB32) interrupt.
Write 1 to clear.
0 No such occurrence.
1 The corresponding buffer has successfully completed transmission or reception.
29.3.4.10 Interrupt Flags 1 Register (CANx_IFLAG1)
This register defines the flags for 32 message buffer interrupts and FIFO interrupts. It contains one
interrupt flag bit per buffer. Each successful transmission or reception sets the corresponding
CANx_IFLAG1 bit. If the corresponding CANx_IMASK1 bit is set, an interrupt is generated. The
interrupt flag must be cleared by writing it to ‘1’. Writing ‘0’ has no effect.
When the AEN bit in the CANx_MCR register is set (Abort enabled), while the CANx_IFLAG1 bit is set
for a MB configured as Tx, the writing access done by CPU into the corresponding MB is blocked.
When the FEN bit in the CANx_MCR register is set (FIFO enabled), the function of the eight least
significant interrupt flags (BUF7I – BUF0I) is changed to support the FIFO operation. BUF7I, BUF6I and
BUF5I indicate operating conditions of the FIFO, while BUF4I to BUF0I are not used.
Offset: Base + 0x0030
Access: User read/write
0
R _BUF
W ^31I
Reset 0
1
BUF
30I
0
2
BUF
29I
0
3
BUF
28I
0
4
BUF
27I
0
5
BUF
26I
0
6
BUF
25I
0
7
BUF
24I
0
8
BUF
23I
0
9
BUF
22I
0
10
BUF
21I
0
11
BUF
20I
0
12
BUF
19I
0
13
BUF
18I
0
14
BUF
17I
0
15
BUF
16I
0
16
R _BUF
W ^15I
Reset 0
17
BUF
14I
0
18
BUF
13I
0
19
BUF
12I
0
20
BUF
11I
0
21
BUF
10I
0
22
BUF
9I
0
23
BUF
8I
0
24
BUF
7I
0
25
BUF
6I
0
26
BUF
5I
0
27
BUF
4I
0
28
BUF
3I
0
29
BUF
2I
0
30
BUF
1I
0
31
BUF
0I
0
Figure 29-14. Interrupt Flag 1 Register (CANx_IFLAG1)
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
29-25