PXN20RM Datasheet, PDF (983/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Deserial – Serial Peripheral Interface (DSPI)
Table 30-34. DSPI Interrupt and DMA Request Conditions (continued)
Condition
Attempt to transmit with an empty transmit FIFO
RX FIFO is not empty
Frame received while receive FIFO is full
Flag
TFUF
RFDF
RFOF
Interrupt
X
X
X
DMA
X
Each condition has a flag bit in the DSPI Status Register (DSPI_SR) and an Request Enable bit in the DSPI
DMA/Interrupt Request Select and Enable Register (DSPI_RSER). The TX FIFO Fill Flag (TFFF) and
RX FIFO Drain Flag (RFDF) generate interrupt requests or DMA requests depending on the TFFF_DIRS
and RFDF_DIRS bits in the DSPI_RSER. See Table 23-4 for the DSPI DMA channel assignments and
Table 10-12 for the DSPI interrupt vectors.
30.4.12.1 End of Queue Interrupt Request (EOQF)
The end of queue request indicates that the end of a transmit queue is reached. The end of queue request
is generated when the EOQ bit in the executing SPI command is asserted and the EOQF_RE bit in the
DSPI_RSER is asserted. See the EOQ bit description in Section 30.3.2.4, DSPI Status Register
(DSPI_SR). Refer to Figure 30-29 and Figure 30-30 that illustrate when EOQF is set.
30.4.12.2 Transmit FIFO Fill Interrupt or DMA Request (TFFF)
The transmit FIFO fill request indicates that the TX FIFO is not full. The transmit FIFO fill request is
generated when the number of entries in the TX FIFO is less than the maximum number of possible entries,
and the TFFF_RE bit in the DSPI_RSER is asserted. The TFFF_DIRS bit in the DSPI_RSER selects
whether a DMA request or an interrupt request is generated.
30.4.12.3 Transfer Complete Interrupt Request (TCF)
The transfer complete request indicates the end of the transfer of a serial frame. The transfer complete
request is generated at the end of each frame transfer when the TCF_RE bit is set in the DSPI_RSER. See
the TCF bit description in Section 30.3.2.4, DSPI Status Register (DSPI_SR). Refer to Figure 30-29 and
Figure 30-30 that illustrate when TCF is set.
30.4.12.4 Transmit FIFO Underflow Interrupt Request (TFUF)
The transmit FIFO underflow request indicates that an underflow condition in the TX FIFO has occurred.
The transmit underflow condition is detected only for DSPI blocks operating in slave mode and SPI
configuration. The TFUF bit is set when the TX FIFO of a DSPI operating in slave mode and SPI
configuration is empty, and a transfer is initiated from an external SPI master. If the TFUF bit is set while
the TFUF_RE bit in the DSPI_RSER is asserted, an interrupt request is generated.
30.4.12.5 Receive FIFO Drain Interrupt or DMA Request (RFDF)
The receive FIFO drain request indicates that the RX FIFO is not empty. The receive FIFO drain request
is generated when the number of entries in the RX FIFO is not zero, and the RFDF_RE bit in the
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PXN20 Microcontroller Reference Manual, Rev. 1
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