PXN20RM Datasheet, PDF (203/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

System Integration Unit (SIU)
Offset: SIU_BASE + 0x002C
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R _{NFEE01 NFEE11} 0
0
0
0
0
0
00
0
0
00
0
0
W
Reset 0
0
0
0
0
0
0000000
000
16
R _IFEE
W ¹⁵
17
IFEE
14
18
19
20
21
22
23
24
25
26
27
28
29
30
31
IFEE IFEE IFEE IFEE IFEE IFEE IFEE IFEE IFEE IFEE IFEE IFEE IFEE IFEE
13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0
0
0
0
0
0
0000000000
1 _{Once written, the NFEEn bits cannot be changed until the next reset.}
Figure 8-11. IRQ Falling-Edge Event Enable Register (SIU_IFEER)
Table 8-13. SIU_IFEER Field Descriptions
Field
Function
NFEEn
NMI Falling-Edge Event Enable n. These write-once bits enable rising-edge triggered events on the corresponding
NMIn input.
0 Falling edge event disabled.
1 Falling edge event enabled.
Note: Once written, the NFEEn bits cannot be changed until the next reset.
IFEEn IRQ Falling-Edge Event Enable n. Enables falling-edge triggered events on the corresponding IRQn pin.
0 Falling edge event disabled.
1 Falling edge event enabled.
8.3.2.11 External IRQ Digital Filter Register (SIU_IDFR)
The SIU_IDFR specifies the amount of digital filtering on the IRQ0–IRQ15 pins. The digital filter length
field specifies the number of system clocks that define the period of the digital filter and the minimum time
a signal must be held in the active state on the IRQ pins to be recognized as an edge-triggered event.
Offset: SIU_BASE + 0x0030
Access: User read/write
0
R0
W
Reset 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
00000
0000
0
0
0
0
0
0
00000
0000
16
R0
W
Reset 0
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
00000
DFL
0
0
0
0
0
0
00000
0000
Figure 8-12. External IRQ Digital Filter Register (SIU_IDFR)
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
8-21