PXN20RM Datasheet, PDF (1136/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

IEEE 1149.1 Test Access Port Controller (JTAGC)
JCOMP
Power-on
reset
TMS
TCK
Test access port (TAP)
controller
5-bit TAP instruction register
5-bit TAP instruction decoder
TDI
1-bit bypass register
32-bit device identification register
TDO
Nexus Port Controller TDO
e200Z6 TDO
e200Z0 TDO
Daisy Chained
e200Z6 and e200Z0 TDO
TEST_CNTL register
Figure 35-1. JTAGC Block Diagram
35.1.1.1 Individual and Multi-Core Debug
When daisy chaining a JTAG interface (see Figure 35-2), two separate commands can be shifted into the
different cores serially. This allows start (go) commands or step commands to be input to the cores in
parallel. Commands are shifted in during the JTAG SHIFT_IR state and are executed when the
UPDATE_IR state is reached in the TAP state diagram.
35-2
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor