PXN20RM Datasheet, PDF (1133/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Analog-to-Digital Converter (ADC)
34.4.8 External Decode Signals Delay
The ADC provides three external decode signals used to select which of the 32 group 2 channels has to be
converted. In order to take into account the control switching time of the external analog mux a Decode
Signals Delay register is provided. Writing that register allows to program the delay between the decoding
signal selection and the actual start of conversion
34.4.9 Power Down Mode
The analog part of the ADC can be put in low power mode by setting the PWDN bit in MCR. After
ipg_hard_async_reset_b is released the ADC analog module is kept in power down mode by default, so
this state must be exited before starting any operation by resetting the appropriate bit in MCR. When in
power down mode, no offset cancellation or conversion can be started. If a ctu_trigger pulse is received
during power-down, it is discarded.
If a conversion or an offset cancellation is ongoing then ADC hard macrocell cannot be put immediately
into the power down mode. The ongoing operation must be allowed to complete or be aborted manually
(by resetting the NSTART or OFFCANC bit) and only then may the PWDN bit in the MCR register be
cleared. A normal or an injected conversion can be aborted using the ABORTCHAIN function.
If the PWDN is set while a normal conversion is running, the ADC completes the current channel
conversion before entering power-down. As a consequence, PWDN bit of CSR is set only after the running
conversion has finished.
If the CTU is enabled and CTUSTART bit is ‘1’ then the PWDN bit cannot be set. When CTU trigger mode
is enabled, the application has to wait for the end of conversion (CTUSTART bit automatically reset).
When CTU control mode is enabled, before entering power-down the application needs to reset CTUEN
bit, too.
After the power down phase is completed, the process ongoing before the power down phase must be
restarted manually (by setting the appropriate START/OFFCANC bit).
34.4.10 Auto Clock Off Mode
To reduce the power consumption during the IDLE mode of operation (without going into power down
mode), an “auto-clock-off” feature can be enabled by setting the MCR[ACKO] bit. When enabled, the
analog clock is automatically switched off when no operation is ongoing, that is, no offset cancellation or
offset refresh in idle phase or conversion is programmed by the user.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
34-53