PXN20RM Datasheet, PDF (1239/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Nexus Development Interface (NDI)
information allows the development tool to interpret any preceding instruction count or history
information in the proper context.
• Whenever the CPU crosses a page boundary that results in an execution mode switch into or out
of a sequence of VLE instructions, a PCM is generated. The PCM effectively breaks up any
running instruction count and history information between the two modes of operation so that the
instruction count and history information can be processed by the development tool in the proper
context.
• When using program trace in history mode, when a direct branch results in an execution mode
switch into or out of a sequence of VLE instructions, a PCM is generated. The PCM effectively
breaks up any running history information between the two modes of operation so that the history
information can be processed by the development tool in the proper context.
Program correlation is messaged out in the following format:
5
4
3
2
1
HIST
I-CNT
EVCODE
SRC
MSB 1–32 bits
1–8 bits
4 bits
4 bits
Max length = 54 bits; Min length = 16 bits
Figure 36-67. Program Correlation Message Format
TCODE (100001)
6 bits LSB
BTM Overflow Error Messages
An error message occurs when a new message cannot be queued due to the message queue being full. The
FIFO discards incoming messages until it has completely emptied the queue. Once emptied, an error
message is queued. The error encoding indicates which types of messages attempted to be queued while
the FIFO was being emptied.
If only a program trace message attempts to enter the queue while it is being emptied, the error message
incorporates the program trace only error encoding (00001). If both OTM and program trace messages
attempt to enter the queue, the error message incorporates the OTM and program trace error encoding
(00111). If a watchpoint also attempts to be queued while the FIFO is being emptied, then the error
message incorporates error encoding (01000).
NOTE
The OVC bits within the DC1 register can be set to delay the CPU in order
to alleviate (but not eliminate) potential overrun situations.
Error information is messaged out in the following format:
:
3
2
1
ECODE (00001 / 00111 / 01000)
SRC
TCODE (001000)
MSB
5 bits
4 bits
Fixed length = 15 bits
Figure 36-68. Error Message Format
6 bits LSB
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
36-89