PXN20RM Datasheet, PDF (286/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Interrupts and Interrupt Controller (INTC)
Table 10-10. INTC Priority Select Register Address Offsets
INTC_PSRn_n
INTC_PSR108_111
INTC_PSR112_115
INTC_PSR116_119
INTC_PSR120_123
INTC_PSR124_127
INTC_PSR128_131
INTC_PSR132_135
INTC_PSR136_139
INTC_PSR140_143
INTC_PSR144_147
INTC_PSR148_151
INTC_PSR152_155
INTC_PSR156_159
Offset Address
0x00AC
0x00B0
0x00B4
0x00B8
0x00BC
0x00C0
0x00C4
0x00C8
0x00CC
0x00D0
0x00D4
0x00D8
0x00DC
INTC_PSRn_n
INTC_PSR268_271
INTC_PSR272_275
INTC_PSR276_279
INTC_PSR280_283
INTC_PSR284_287
INTC_PSR288_291
INTC_PSR292_295
INTC_PSR296_299
INTC_PSR300_303
INTC_PSR304_307
INTC_PSR308_311
INTC_PSR312_315
Offset Address
0x014C
0x0150
0x0154
0x0158
0x015C
0x0160
0x0164
0x0168
0x016C
0x0170
0x0174
0x0178
The priority select registers support the selection of an individual priority for each source of interrupt
request, and whether the interrupt request is to be sent to processor 0 (Z6), processor 1, (Z0) or both. The
unique vector of each peripheral or software settable interrupt request determines which INTC_PSRn_n is
assigned to that interrupt request. The software settable interrupt requests 0–7 are assigned vectors 0–7,
and their priorities are configured in INTC_PSR0_3 and INTC_PSR4_7, respectively. The peripheral
interrupt requests are assigned vectors 8–315, and their priorities are configured in INTC_PSR8_11
through INTC_PSR312_315, respectively (see Section 10.4.1, External Interrupt Request Sources,).
NOTE
The PRC_SELn or PRIn field of an INTC_PSRn_n must not be modified
while the corresponding peripheral or software settable interrupt request is
asserted.
Table 10-11. Selected Processor for Interrupt Request
PRC_SELn
Meaning
00
Interrupt request sent to processor 0 (Z6)
01
Interrupt request sent to both processors
10
Reserved
11
Interrupt request sent to processor 1 (Z0)
10-18
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor