PXN20RM Datasheet, PDF (1201/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Nexus Development Interface (NDI)
:
5
4
3
2
1
HIST
F-ADDR
I-CNT
SRC
TCODE (011101)
MSB 1–32 bits
1–32 bits
1–8 bits
4 bits
6 bits LSB
Max length = 82 bits; Min length = 13 bits
Figure 36-35. Indirect Branch History with Sync. Message Format
Exception conditions that result in program trace synchronization are summarized in Table 36-34.
Table 36-34. Program Trace Exception Summary
Exception Condition
Exception Handling
System Reset Negation
At the negation of JTAG reset (JCOMP), queue pointers, counters, state machines, and registers
within the Nexus3+ module are reset. Upon the first branch out of system reset (if program trace
is enabled), the first program trace message is a direct/indirect branch with sync. message.
Program Trace Enabled The first program trace message (after program trace has been enabled) is a synchronization
message.
Exit from Low Power/Debug Upon exit from a low power mode or debug mode, the next direct/indirect branch is converted to
a direct/indirect branch with sync. message.
Queue Overrun
An error message occurs when a new message cannot be queued due to the message queue
being full. The FIFO discards messages until it has completely emptied the queue. Once
emptied, an error message is queued. The error encoding indicates which types of messages
attempted to be queued while the FIFO was being emptied. The next BTM message in the queue
is a direct/indirect branch with sync. message.
Periodic Program Trace
Sync.
A forced synchronization occurs periodically after 255 program trace messages have been
queued. A direct/indirect branch with sync. message is queued. The periodic program trace
message counter then resets.
Event In
If the Nexus module is enabled, an EVTI assertion initiates a direct/indirect branch with sync.
message upon the next direct/indirect branch (if program trace is enabled and the EIC bits of the
DC1 register have enabled this feature).
Sequential Instruction Count
Overflow
When the sequential instruction counter reaches its maximum count (as many as 255 sequential
instructions may be executed), a forced synchronization occurs. The sequential counter then
resets. A program trace direct/indirect branch with sync.message is queued upon execution of
the next branch.
Attempted Access to Secure For devices that implement security, any attempted branch to secure memory locations
Memory
temporarily disables program trace, and causes the corresponding BTM to be lost. The following
direct/indirect branch queues a direct/indirect branch with sync. message. The count value within
this message is inaccurate since the re-enable of program trace is not necessarily aligned on an
instruction boundary.
Collision Priority
All messages have the following priority: WPM  OTM  BTM  DTM. A BTM message that
attempts to enter the queue at the same time as a watchpoint message or ownership trace
message is lost. An error message is sent indicating the BTM was lost. The following
direct/indirect branch queues a direct/indirect branch with sync. message. The count value within
this message reflects the number of sequential instructions executed after the last successful
BTM Message was generated. This count includes the branch that did not generate a message
due to the collision.
Execution Mode Switch Whenever the CPU switches execution mode into or out of a sequence of VLE instructions, the
next branch trace message is a Direct/Indirect Branch w/ Sync Message.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
36-51