PXN20RM Datasheet, PDF (954/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Deserial – Serial Peripheral Interface (DSPI)
Table 30-23. DSPI_SDR Field Descriptions
Field
TSBCNT
DPCS1_x
Description
Timed Serial Bus Operation Count. When TSBC is set, TSBCNT defines the length of the TSB frame. A number
between 4 and 32.
The TSBCNT field selects number of bits to be shifted out during a transfer in TSB operation. The field sets the
number of SCK cycles that the bus master generates to complete the transfer. The number of SCK cycles used
is one more than the value in the TSBCNT field. The number of SCK cycles defined by TSBCNT must be equal
to or greater than the frame size.
DSI Peripheral Chip Select 0–7. These bits define the CS to assert for the second part of the DSI frame when
operating in TSB configuration with dual receiver. The DPCS1 bits select which of the PCS signals to assert
during the second DSI transfer. The DPCS1 bits only control the assertions of the PCS signals in DSI master
mode when in TSB configuration.
0 Negate PCS[x].
1 Assert PCS[x].
30.4 Functional Description
The DSPI supports full-duplex, synchronous serial communications between the MCU and peripheral
devices. The DSPI can also be used to reduce the number of pins required for I/O by serializing and
deserializing as many as 16 parallel input/output signals from the eMIOS. All communications are through
an SPI-like protocol. Specifically in the TSB configuration, the DSPI can serialize as many as 32 parallel
input signals or 32 registered bits.
The DSPI has three configurations:
• SPI configuration, in which the DSPI operates as a basic SPI or a queued SPI.
• DSI configuration, in which the DSPI serializes and deserializes parallel input/output signals or
bits from memory-mapped registers.
• CSI configuration, in which the DSPI combines the functionality of the SPI and DSI
configurations.
The DCONF field in the DSPI_MCR register determines the DSPI configuration. See Table 30-3 for the
DSPI configuration values.
The DSPI_CTARn registers hold clock and transfer attributes. The manner in which a CTAR is selected
depends on the DSPI configuration (SPI, DSI, or CSI). The SPI configuration can select which CTAR to
use on a frame-by-frame basis by setting the CTAS field in the DSPI_PUSHR. The DSI configuration
statically selects which CTAR to use. In CSI configuration, priority logic determines if SPI data or DSI
data is transferred. The type of data transferred (whether DSI or SPI) dictates which CTAR the CSI
configuration uses. See Section 30.3.2.3, DSPI Clock and Transfer Attributes Registers 0–7
(DSPI_CTARn), for information on DSPI_CTARn fields.
The 16-bit shift register in the master and the 16-bit shift register in the slave are linked by the SOUT and
SIN signals to form a distributed 32-bit register. The master and slave use 16-bit shift registers regardless
the TSBC bit is asserted in the DSPI_DSICR register. When a data transfer operation is performed, data is
serially shifted a pre-determined number of bit positions. Because the registers are linked, data is
exchanged between the master and the slave; the data that was in the master’s shift register is now in the
30-28
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor