PXN20RM Datasheet, PDF (113/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Chapter 4
Resets
4.1 Introduction
This chapter describes the resets and reset sources for the PXN20.
The reset sources supported in the PXN20 are:
• Power-on reset (POR)
• Low-voltage inhibit (LVI) reset
• External reset
• Loss-of-lock reset
• Loss-of-clock reset
• Watchdog timer reset
• JTAG reset
• Checkstop reset (both Z6 and Z0 cores)
• Software-system reset
All reset sources are processed by the reset controller, which is located in the SIU module (Chapter 8,
System Integration Unit (SIU)). The reset controller monitors the reset input sources. Upon detection of a
reset event, the reset controller resets internal logic and controls the assertion of the RESET pin.
The MCU is clocked by the 16 MHz IRC clock after any reset.
The reset status register (SIU_RSR) gives the source, or sources, of the last reset and is updated for all reset
sources except JTAG reset
The BOOTCFG pin controls the MCU boot sequence after any reset. If the pin is driven low during the
MCU reset, the MCU boots from internal flash and the Reset Configuration Halfword (RCHW) controls
the boot sequence. The RCHW needs to be programmed by user in internal flash in one of predefined
locations together with the user application start address.
If the pin is driven high, the BAM executes the serial boot sequence.
See Chapter 9, Boot Assist Module (BAM), for more details about the boot procedures.
4.2 External Signal Description
Refer to Table 3-1 and Section 3.4, Detailed Signal Description, for signal properties.
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
4-1