PXN20RM Datasheet, PDF (465/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Error Correction Status Module (ECSM)
19.2.2.2 ECC Configuration Register (ECR)
The ECC configuration register is an 8-bit control register for specifying which types of memory errors
are reported. In all systems with ECC, the occurrence of a non-correctable error causes the current access
to be terminated with an error condition. In many cases, this error termination is reported directly by the
initiating bus master. However, there are certain situations where the occurrence of this type of
non-correctable error is not reported by the master. Examples include speculative instruction fetches that
are discarded due to a change-of-flow operation and buffered operand writes. The ECC reporting logic in
the ECSM provides an optional error interrupt mechanism to signal all non-correctable memory errors. In
addition to the interrupt generation, the ECSM captures specific information (memory address, attributes
and data, bus master number, etc.) that may be useful for subsequent failure analysis.
See Figure 19-2 and Table 19-4 for the ECC configuration register definition.
Offset: ECSM_BASE_ADDR + 0x0043
0
1
2
3
4
5
R
0
0
0
0
EPR1BR EPF1BR
W
Reset
0
0
0
0
0
0
Figure 19-2. ECC Configuration (ECR) Register
Access: User read/write
6
7
EPRNCR EPFNCR
0
0
Table 19-4. ECR Field Descriptions
Field
Description
EPR1BR
Enable Platform RAM 1-bit Reporting. The occurrence of a single-bit RAM correction generates an ECSM ECC
interrupt request as signalled by the assertion of ESR[PR1BC]. The address, attributes and data are also captured
in the PREAR, PRESR, PREMR, PREAT, and PREDR registers.
0 Reporting of single-bit platform RAM corrections is disabled.
1 Reporting of single-bit platform RAM corrections is enabled.
EPF1BR
Enable Platform Flash 1-bit Reporting. The occurrence of a single-bit flash correction generates an ECSM ECC
interrupt request as signalled by the assertion of ESR[PF1BC]. The address, attributes, and data are also captured
in the PFEAR, PFEMR, PFEAT, and PFEDR registers.
0 Reporting of single-bit platform flash corrections is disabled.
1 Reporting of single-bit platform flash corrections is enabled.
EPRNCR
Enable Platform RAM Non-Correctable Reporting. The occurrence of a non-correctable multi-bit RAM error
generates an ECSM ECC interrupt request as signaled by the assertion of ESR[PRNCE]. The faulting address,
attributes, and data in either the 512 KB or 80 KB array are also captured in the PREAR, PRESR, PREMR, PREAT,
and PREDR registers.
0 Reporting of non-correctable platform RAM errors is disabled.
1 Reporting of non-correctable platform RAM errors is enabled.
EPFNCR
Enable Platform Flash Non-Correctable Reporting. The occurrence of a non-correctable multi-bit flash error
generates an ECSM ECC interrupt request as signaled by the assertion of ESR[PFNCE]. The faulting address,
attributes, and data are also captured in the PFEAR, PFEMR, PFEAT, and PFEDR registers.
0 Reporting of non-correctable platform flash errors is disabled.
1 Reporting of non-correctable platform flash errors is enabled.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
19-5