PXN20RM Datasheet, PDF (407/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

e200z0 Core (Z0)
— SPRG0–SPRG1. The SPRG0–SPRG1 registers are provided for operating system or interrupt
handler use.
— Exception Syndrome Register (ESR). The ESR register provides a syndrome to differentiate
between the different kinds of exceptions which can generate the same interrupt.
— Interrupt Vector Prefix Register (IVPR). This register together with hardwired offsets which
replace the IVOR0-15 registers provide the address of the interrupt handler for different classes
of interrupts.
— Save/Restore Register 0 (SRR0). The SRR0 register is used to save machine state on a
non-critical interrupt, and contains the address of the instruction at which execution resumes
when an se_rfi instruction is executed at the end of a non-critical class interrupt handler routine.
— Critical Save/Restore Register 0 (CSRR0). The CSRR0 register is used to save machine state
on a critical interrupt, and contains the address of the instruction at which execution resumes
when an se_rfci instruction is executed at the end of a critical class interrupt handler routine.
— Save/Restore Register 1 (SRR1). The SRR1 register is used to save machine state from the
MSR on non-critical interrupts, and to restore machine state when se_rfi executes.
— Critical Save/Restore Register 1 (CSRR1). The CSRR1 register is used to save machine state
from the MSR on critical interrupts, and to restore machine state when se_rfci executes.
• Debug Facility Registers
— Debug Control Registers (DBCR0–DBCR2). These registers provide control for enabling and
configuring debug events.
— Debug Status Register (DBSR). This register contains debug event status.
— Instruction Address Compare registers (IAC1–IAC4). These registers contain addresses and/or
masks which are used to specify Instruction Address Compare debug events.
— Data Address Compare registers (DAC1–2). These registers contain addresses and/or masks
which are used to specify Data Address Compare debug events.
— e200 does not implement the Data Value Compare registers (DVC1 and DVC2).
14.3.2 e200-Specific Special Purpose Registers
The Power Architecture Book E architecture allows implementation-specific special purpose registers.
Those incorporated in the e200 core are as follows:
14.3.2.1 User-Level Registers
The user-level registers can be accessed by all software with either user or supervisor privileges. They
include the following:
• The L1 Cache Configuration register (L1CFG0). This read-only register allows software to query
the configuration of the L1 Cache. For the e200z0, this register returns all zeros indicating no cache
is present.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
14-9