PXN20RM Datasheet, PDF (908/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Controller Area Network (FlexCAN)
Field
BUFnM
Table 29-12. CANx_IMASK2 Field Descriptions
Description
Message Buffer n Mask. Enables or disables the respective FlexCAN message buffer (MB63 to MB32) Interrupt.
0 The corresponding buffer Interrupt is disabled.
1 The corresponding buffer Interrupt is enabled.
Note: Setting or clearing a bit in the CANx_IMASK2 register can assert or negate an interrupt request,
respectively.
29.3.4.8 Interrupt Masks 1 Register (CANx_IMASK1)
This register allows to enable or disable any number of a range of 32 message buffer interrupts. It contains
one interrupt mask bit per buffer, enabling the CPU to determine which buffer generates an interrupt after
a successful transmission or reception (i.e., when the corresponding CANx_IFLAG1 bit is set).
Offset: Base + 0x0028
Access: User read/write
0
R _BUF
W ^31M
Reset 0
1
BUF
30M
0
2
BUF
29M
0
3
BUF
28M
0
4
BUF
27M
0
5
BUF
26M
0
6
BUF
25M
0
7
BUF
24M
0
8
BUF
23M
0
9
BUF
22M
0
10
BUF
21M
0
11
BUF
20M
0
12
BUF
19M
0
13
BUF
18M
0
14
BUF
17M
0
15
BUF
16M
0
16
R _BUF
W ^15M
Reset 0
17
BUF
14M
0
18
BUF
13M
0
19
BUF
12M
0
20
BUF
11M
0
21
BUF
10M
0
22
BUF
9M
0
23
BUF
8M
0
24
BUF
7M
0
25
BUF
6M
0
26
BUF
5M
0
27
BUF
4M
0
28
BUF
3M
0
29
BUF
2M
0
30
BUF
1M
0
31
BUF
0M
0
Figure 29-12. Interrupt Masks 1 Register (CANx_IMASK1)
Table 29-13. CANx_IMASK1 Field Descriptions
Field
BUFnM
Description
Message Buffer n Mask. Enables or disables the respective FlexCAN message buffer (MB31 to MB0) Interrupt.
0 The corresponding buffer Interrupt is disabled.
1 The corresponding buffer Interrupt is enabled.
Note: Setting or clearing a bit in the CANx_IMASK1 register can assert or negate an interrupt request,
respectively.
29.3.4.9 Interrupt Flags 2 Register (CANx_IFLAG2)
This register defines the flags for 32 message buffer interrupts. It contains one interrupt flag bit per buffer.
Each successful transmission or reception sets the corresponding CANx_IFLAG2 bit. If the corresponding
CANx_IMASK2 bit is set, an interrupt is generated. The interrupt flag must be cleared by writing it to ‘1’.
Writing ‘0’ has no effect.
When the AEN bit in the CANx_MCR is set (abort enabled), while the CANx_IFLAG2 bit is set for a MB
configured as Tx, the writing access done by CPU into the corresponding MB is blocked.
29-24
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor