PXN20RM Datasheet, PDF (985/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Deserial – Serial Peripheral Interface (DSPI)
ipg_enable_clk is negated, the DSPI is in a dormant state, but the memory mapped registers are still
accessible. Certain read or write operations have a different affect when the DSPI is in the module disable
mode. Reading the RX FIFO pop register does not change the state of the RX FIFO. Likewise, writing to
the TX FIFO push register does not change the state of the TX FIFO. Clearing either of the FIFOs has no
effect in the module disable mode. Changes to the DIS_TXF and DIS_RXF fields of the DSPI_MCR has
no effect in the module disable mode. In the module disable mode, all status bits and register flags in the
DSPI return the correct values when read, but writing to them has no effect. Writing to the DSPI_TCR
during module disable mode has no effect. Interrupt and DMA request signals cannot be cleared while in
the module disable mode.
30.4.13.3 Slave Interface Signal Gating
The DSPI’s module enable signal is used to gate slave interface signals such as address, byte enable,
read/write and data. This prevents toggling slave interface signals from consuming power unless the DSPI
is accessed. The module enable signal can also be used to gate the clock (ipg_clk_s) to the
memory-mapped logic.
30.5 Initialization/Application Information
30.5.1 How to Change Queues
DSPI queues are not part of the DSPI module, but the DSPI includes features in support of queue
management. Queues are primarily supported in SPI configuration. This section presents an example of
how to change queues for the DSPI.
1. The last command word from a queue is executed. The EOQ bit in the command word is set to
indicate to the DSPI that this is the last entry in the queue.
2. At the end of the transfer, corresponding to the command word with EOQ set is sampled, the EOQ
flag (EOQF) in the DSPI_SR is set.
3. Setting the EOQF flag disables both serial transmission and reception of data, putting the DSPI in
the STOPPED state. The TXRXS bit is negated to indicate the STOPPED state.
4. The eDMA continues to fill TX FIFO until it is full or step 5 occurs.
5. Disable DSPI DMA transfers by disabling the DMA enable request for the DMA channel assigned
to TX FIFO and RX FIFO. This is done by clearing the corresponding DMA enable request bits in
the eDMA controller.
6. Ensure all received data in RX FIFO has been transferred to memory receive queue by reading the
RXCNT in DSPI_SR or by checking RFDF in the DSPI_SR after each read operation of the
DSPI_POPR.
7. Modify DMA descriptor of TX and RX channels for new queues.
8. Flush TX FIFO by writing a 1 to the CLR_TXF bit in the DSPI_MCR, Flush RX FIFO by writing
a 1 to the CLR_RXF bit in the DSPI_MCR.
9. Clear transfer count either by setting CTCNT bit in the command word of the first entry in the new
queue or via CPU writing directly to SPI_TCNT field in the DSPI_TCR.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
30-59