PXN20RM Datasheet, PDF (486/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Software Watchdog Timer (SWT)
The SWT_TO register holds the watchdog time-out period in clock cycles unless the value is less than
0x100, in which case the time-out period is set to 0x100. This time-out period is loaded into an internal
32-bit down counter when the SWT is enabled and each time a valid service operation is performed. The
SWT_CR[CSL] bit selects which clock (system or oscillator) is used to drive the down counter.
NOTE
The default value of SWT_TO is updated by the BAM code during the serial
download routine. See Section 9.3.3.2, Serial-Boot Mode Features, for
more details.
The configuration of the SWT can be locked through use of either a soft lock or a hard lock. In either case,
when locked the SWT_CR, SWT_TO, SWT_WN, and SWT_SK registers are read-only. The hard lock is
enabled by setting the SWT_CR[HLK] bit which can only be cleared by a reset. The soft lock is enabled
by setting the SWT_CR[SLK] bit and is cleared by writing the unlock sequence to the service register. The
unlock sequence is a write of 0xC520 followed by a write of 0xD928 to the SWT_SR[WSC] field. There
is no timing requirement between the two writes. The unlock sequence logic ignores service sequence
writes and recognizes the 0xC520, 0xD928 sequence regardless of previous writes. The unlock sequence
can be written at any time and does not require the SWT_CR[WEN] bit to be set.
When enabled, the SWT requires periodic execution of a servicing operation which consists of writing two
values to the SWT_SR. Writing the proper sequence of values loads the internal down counter with the
time-out period. There is no timing requirement between the two writes and the service sequence logic
ignores unlock sequence writes. If the SWT_CR[KEY] bit is zero, the fixed sequence 0xA602, 0xB480 is
written to the SWT_SR[WSC] field to service the watchdog. If the SWT_CR[KEY] bit is set, then two
pseudorandom keys are written to the SWT_SR[WSC] field to service the watchdog. The key values are
determined by the pseudorandom key generator defined in Equation 20-1. This algorithm generates a
sequence of 2¹⁶ different key values before repeating. The state of the key generator is held in the
SWT_SK register. For example, if SWT_SK[SK] is 0x0100 then the service sequence keys are 0x1103,
0x2136. In this mode, each time a valid key is written to the SWT_SR register, the SWT_SK register is
updated. So, after servicing the watchdog by writing 0x1103 and then 0x2136 to the SWT_SR[WSC] field,
SWT_SK[SK] is 0x2136 and the next key sequence is 0x3499, 0x7E2C.
SK_n+1 = (17*SK_n+3) mod 2¹⁶
Pseudorandom Key Generator
Eqn. 20-1
Accesses to SWT registers occur with no peripheral bus wait states. However, due to synchronization logic
in the SWT design, recognition of the service sequence or configuration changes may require as many as
3 system plus 7 counter clock cycles.
If window mode is enabled (SWT_CR[WND] bit is set), the service sequence must be performed in the
last part of the time-out period defined by the window register. The window is open when the down counter
is less than the value in the SWT_WN register. Outside of this window, service sequence writes are invalid
accesses and generate a bus error or reset depending on the value of the SWT_CR[RIA] bit. For example,
if the SWT_TO register is set to 5000 and SWT_WN register is set to 1000 then the service sequence must
be performed in the last 20% of the time-out period. There is a short lag in the time it takes for the window
20-8
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor