PXN20RM Datasheet, PDF (1225/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Nexus Development Interface (NDI)
Table 36-47 shows the event code encodings used for certain messages.
Table 36-47. Event Code Encoding (TCODE = 33)
Event Code
Description
0000
0001
Entry into Debug Mode
Entry into Low Power Mode (CPU only)¹
0010–0011 Reserved for future functionality
0100
Disabling Program Trace
0101–1111 Reserved for future functionality
1 _{The device enters Low Power Mode when the Nexus stall mode is enabled}
(NEXUS2_DC1[OVC] = 0b011) and a trace message is in danger of over-flowing
the Nexus queue.
36.7.6 Nexus2+ Memory Map
This section describes the Nexus2+ programmer’s model. Nexus2+ registers are accessed using the
JTAG/OnCE port in compliance with IEEE 1149.1. See Section 36.7.8, Nexus2+ Register Access via
JTAG / OnCE for details on Nexus2+ register access.
NOTE
Nexus2+ registers and output signals are numbered using bit 0 as the least
significant bit. This bit ordering is consistent with the ordering defined by
the IEEE-ISTO 5001 standard.
Table 36-48 details the register map for the Nexus2+ module.
Table 36-48. Nexus2+ Memory Map
Index
Register Description
Read Address¹ Write Address¹ Section/Page
0x02 e200z0 Development Control1 (PPC_DC1)
0x04
0x05
36.7.7.1/36-76
0x03 e200z0 Development Control2 (PPC_DC2)
0x06
0x07
36.7.7.1/36-76
0x04 e200z0 Development Status (PPC_DS)
0x08
—
36.7.7.2/36-78
0x07 e200z0 Read/Write Access Control/Status (Nexus2_RWCS)
0x0E
0x0F
36.7.7.3/36-78
0x09 e200z0 Read/Write Access Address (Nexus2_RWA)
0x12
0x13
36.7.7.4/36-80
0x0A e200z0 Read/Write Access Data (Nexus2_RWD)
0x14
0x15
36.7.7.5/36-80
0x0B e200z0 Watchpoint Trigger (PPC_WT)
0x16
0x17
36.7.7.6/36-81
0xC – 0x3F Reserved
1 _{See Section 36.5.5.2.3, NPC IEEE 1149.1-2001 (JTAG) TAP, for a description of the read and write address usage for the}
e200z6 and e200z0 Nexus Control/Status registers.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
36-75