PXN20RM Datasheet, PDF (508/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

DMA Channel Multiplexer (DMA_MUX)
Table 23-1. DMA_MUX Memory Map (continued)
Offset from
DMA_MUX_BASE
(0xFFFD_C000)
Register
0x001D
0x001E
0x001F
CHCONFIG29—Channel #29 configuration
CHCONFIG30—Channel #30 configuration
CHCONFIG31—Channel #31 configuration
Access Reset Value Section/Page
R/W
0x00
23.3.2.1/23-4
R/W
0x00
23.3.2.1/23-4
R/W
0x00
23.3.2.1/23-4
23.3.2 Register Descriptions
This section lists the DMA_MUX registers in address order and describes the registers and their bit fields.
23.3.2.1 Channel Configuration Registers (CHCONFIGx)
Each of the 32 DMA channels can be independently enabled/disabled and associated with one of the 59
DMA sources in the system.
Offset: DMA_MUX_BASE + x – 1
Access: User read/write
0
1
2
3
4
5
6
7
R
ENBL
W
TRIG
SOURCE
Reset
0
0
0
0
0
0
0
0
Figure 23-2. Channel Configuration Registers (CHCONFIGx)
Table 23-2. CHCONFIGx Field Descriptions
Field
Description
ENBL
DMA Channel Enable. ENBL enables the DMA channel.
0 DMA channel is disabled. This mode is primarily used during configuration of the DMA_MUX. The DMA has
separate channel enables/disables, which should be used to disable or re-configure a DMA channel.
1 DMA channel is enabled.
TRIG
DMA Channel Trigger Enable (channels 0–7 only). TRIG enables the periodic trigger capability for the DMA channel
0 Triggering is disabled. If triggering is disabled and the ENBL bit is set, the DMA channel routes the specified
source to the DMA channel.
1 Triggering is enabled.
SOURCE DMA Channel Source. SOURCE specifies which DMA source, if any, is routed to a particular DMA channel,
according to Table 23-4.
ENBL
0
1
1
TRIG
X
0
1
Table 23-3. Channel and Trigger Enabling
Function
DMA channel is disabled
DMA channel is enabled with no triggering (transparent)
DMA channel is enabled with triggering
Mode
Disabled mode
Normal mode
Periodic trigger mode
23-4
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor