PXN20RM Datasheet, PDF (211/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

System Integration Unit (SIU)
Table 8-20. GPIO Pin Data Input Register to Pin Mapping
SIU_GPDIn
0_3
4_7
8_11
12_15
16_19
20_23
24_27
28_31
32_35
36_39
40_43
44_47
48_51
52_55
56_59
60_63
64_67
68_71
72_75
76_79
80_83
84_87
88_91
92_95
96_99
100_103
104_107
108_111
112_115
116_119
120_123
124_127
128_131
132_135
136_139
140_143
144_147
148_151
152_154
Address Offset
0x0800
0x0804
0x0808
0x080C
0x0810
0x0814
0x0818
0x081C
0x0820
0x0824
0x0828
0x082C
0x0830
0x0834
0x0838
0x083C
0x0840
0x0844
0x0848
0x084C
0x0850
0x0854
0x0858
0x085C
0x0860
0x0864
0x0868
0x086C
0x0870
0x0874
0x0878
0x087C
0x0880
0x0884
0x0888
0x088C
0x0890
0x0894
0x0898
Pins
PA0–PA3
PA4–PA7
PA8–PA11
PA12–PA15
PB0–PB3
PB4–PB7
PB8–PB11
PB12–PB15
PC0–PC3
PC4–PC7
PC8–PC11
PC12–PC15
PD0–PD3
PD4–PD7
PD8–PD11
PD12–PD15
PE0–PE3
PE4–PE7
PE8–PE11
PE12–PE15
PF0–PF3
PF4–PF7
PF8–PF11
PF12–PF15
PG0–PG3
PG4–PG7
PG8–PG11
PG12–PG15
PH0–PH3
PH4–PH7
PH8–PH11
PH12–PH15
PJ0–PJ3
PJ4–PJ7
PJ8–PJ11
PJ12–PJ15
PK0–PK3
PK4–PK7
PK8–PK10
8.3.2.16 IMUX Select Register 1 (SIU_ISEL1)
The SIU_ISEL1 selects the source for the external interrupt. The selection is made in conjunction with
SIU_ISEL2 and SIU_ISEL2A registers. Figure 8-72 shows how ISEL1, ISEL2, and ISEL2A interact.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
8-29