PXN20RM Datasheet, PDF (1065/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Config I²C for
Master TX
CPU sets
DMAENABLE
Inter-Integrated Circuit Bus Controller Module (I²C)
Start
Generated
CPU writes calling
address to slave
interrupt
generated
Arb Lost or
No ack?
no
yes
ipd_rx_req
generated
CPU handles
condition
no
DMA writes 1
byte of data
DMA written
(n-1) bytes of
data?
yes
CPU clears
DMA enable
CPU writes last
data byte
interrupt
generated
interrupt
generated
CPU clears
MS bit in CR
Stop
generated
Figure 32-14. Flowchart of DMA Mode Master Transmit
32.5.2.2 DMA Mode, Master RX
Figure 32-15 details the exact operation for using a DMA controller to receive n data bytes from a slave.
The first byte (the slave calling address) is always transmitted by the CPU. All subsequent data bytes (apart
from the two last data bytes) can be read by the DMA controller. The last two data bytes must be
transferred by the CPU.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
32-21