PXN20RM Datasheet, PDF (1099/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Analog-to-Digital Converter (ADC)
Address: ADC_BASE + 0x0044
Access: User read/write
0
R _DMA
W ³¹
Reset 0
1
DMA
30
0
2
DMA
29
0
3
DMA
28
0
4
DMA
27
0
5
DMA
26
0
6
DMA
25
0
7
DMA
24
0
8
DMA
23
0
9
DMA
22
0
10
DMA
21
0
11
DMA
20
0
12
DMA
19
0
13
DMA
18
0
14
DMA
17
0
15
DMA
16
0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R _{DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA}
W ^{15 14 13 12 11 10 9}
8
7
6
5
4
3
2
1
0
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 34-15. DMA Channel Select Register 0 (DMAR0)
Table 34-15. DMAR0 Field Descriptions
Field
DMAn
Description
When set, channel n is enabled to transfer data in DMA mode.
34.3.2.15 DMA Channel Select Register 1 (DMAR1)
The DMAR1 register contains the DMA Enable bits for group 1 channels (channels 32–63).
Address: ADC_BASE + 0x0048
Access: User read/write
0
R _DMA
W ⁶³
Reset 0
1
DMA
62
0
2
DMA
61
0
3
DMA
60
0
4
DMA
59
0
5
DMA
58
0
6
DMA
57
0
7
DMA
56
0
8
DMA
55
0
9
DMA
54
0
10
DMA
53
0
11
DMA
52
0
12
DMA
51
0
13
DMA
50
0
14
DMA
49
0
15
DMA
48
0
16
R _DMA
W ⁴⁷
Reset 0
17
DMA
46
0
18
DMA
43
0
19
DMA
44
0
20
DMA
43
0
21
DMA
42
0
22
DMA
41
0
23
DMA
40
0
24
DMA
39
0
25
DMA
38
0
26
DMA
37
0
27
DMA
36
0
28
DMA
35
0
29
DMA
34
0
30
DMA
33
0
31
DMA
32
0
Figure 34-16. DMA Channel Select Register 1 (DMAR1)
Table 34-16. DMAR1 Field Descriptions
Field
DMAn
Description
When set, channel n is enabled to transfer data in DMA mode.
34.3.2.16 DMA Channel Select Register 2 (DMAR2)
The DMAR2 register contains the DMA Enable bits for group 2 channels (channels 64–95).
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
34-19