PXN20RM Datasheet, PDF (785/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Media Local Bus (MLB)
Table 27-11. SMCR Field Descriptions
Field
Description
SMMU
System Masks MLB Unlock. When set, this bit masks system interrupts generated when a MLB unlock is detected.
At reset, MLB unlock events are masked (SMMU = 1).
0 MLB unlock system interrupt is enabled.
1 MLB unlock system interrupt is disabled.
SMML
System Masks MLB Lock. When set, this bit masks system interrupts generated when MLB lock is detected. At reset,
MLB lock events are masked (SMML = 1).
0 MLB lock system interrupt is enabled.
1 MLB lock system interrupt is disabled.
SMSC
System Masks SubCommand. When set, this bit masks system interrupts for the MlbSubCmd (E6h) System
Command.
0 MLB SubCommand system interrupt is enabled.
1 MLB SubCommand system interrupt is disabled.
SMCS System Masks Channel Scan. When set, this bit masks system interrupts for the MlbScan (E4h) System Command.
0 MLB Channel Scan system interrupt is enabled.
1 MLB Channel Scan system interrupt is disabled.
SMNU
System Masks Network Unlock. When set, this bit masks system interrupts for the MOST_Unlock (E2h) System
Command.
0 MLB Network Unlock system interrupt is enabled.
1 MLB Network Unlock system interrupt is disabled.
SMNL
System Masks Network Lock. When set, this bit masks system interrupts for the MOST_Lock (E0h) System
Command.
0 MLB Network Lock system interrupt is enabled.
1 MLB Network Lock system interrupt is disabled.
SMR
System Masks Reset. When set, this bit masks system interrupts for the MlbReset (FEh) System Command.
0 MLB Reset system interrupt is enabled.
1 MLB Reset system interrupt is disabled.
27.3.2.5 Version Control Configuration Register (VCCR)
The Version Control Configuration Register (VCCR) allows system software to verify the version of the
MLB and the user implementation.
Offset: MLB_BASE + 0x001C
Access: User read-only
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
UMA[7:0]
UMI[7:0]
W
Reset 0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
MMA[7:0]
MMI[7:0]
W
Reset 0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
Figure 27-6. Version Control Configuration Register (VCCR)
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
27-13