PXN20RM Datasheet, PDF (527/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Enhanced Direct Memory Access Controller (eDMA)
Table 24-2. eDMA 32-bit Memory Map—Graphical View (continued)
Address
Register
0xFFF4_4024
0xFFF4_4028
0xFFF4_402C
0xFFF4_4030
0xFFF4_4034
0xFFF4_4038 –
0xFFF4_40FC
0xFFF4_4100
0xFFF4_4104
0xFFF4_4108
0xFFF4_410C
0xFFF4_4110
0xFFF4_4114
0xFFF4_4118
0xFFF4_411C
0xFFF4_5000 –
0xFFF4_51FC
0xFFF4_5200 –
0xFFF4_53FC
0xFFF4_5400
eDMA Interrupt Request
(EDMA_IRQRL, channels 31–16)
eDMA Error
(EDMA_ERL, channels 31–16)
eDMA Hardware Request Status
(EDMA_HRSL, channels 31–16)
Reserved
Reserved
Reserved
eDMA Interrupt Request
(EDMA_IRQRL, Channels 15–00)
eDMA Error
(EDMA_ERL, Channels 15–00)
eDMA Hardware Request Status
(EDMA_HRSL, Channels 15–00)
eDMA Channel 0
eDMA Channel 1
eDMA Channel 2
eDMA Channel 3
Priority (EDMA_CPR0) Priority (EDMA_CPR1) Priority (EDMA_CPR2) Priority (EDMA_CPR3)
eDMA Channel 4
eDMA Channel 5
eDMA Channel 6
eDMA Channel 7
Priority (EDMA_CPR4) Priority (EDMA_CPR5) Priority (EDMA_CPR6) Priority EDMA_CPR7)
eDMA Channel 8
eDMA Channel 9
eDMA Channel 10
eDMA Channel 11
Priority (EDMA_CPR8) Priority (EDMA_CPR9) Priority (EDMA_CPR10) Priority (EDMA_CPR11)
eDMA Channel 12
eDMA Channel 13
eDMA Channel 14
eDMA Channel 15
Priority (EDMA_CPR12) Priority (EDMA_CPR13) Priority (EDMA_CPR14) Priority (EDMA_CPR15)
eDMA Channel 16
eDMA Channel 17
eDMA Channel 18
eDMA Channel 19
Priority (EDMA_CPR16) Priority (EDMA_CPR17) Priority (EDMA_CPR18) Priority (EDMA_CPR19)
eDMA Channel 20
eDMA Channel 21
eDMA Channel 22
eDMA Channel 23
Priority (EDMA_CPR16) Priority (EDMA_CPR17) Priority (EDMA_CPR18) Priority (EDMA_CPR19)
eDMA Channel 24
eDMA Channel 25
eDMA Channel 26
eDMA Channel 27
Priority (EDMA_CPR16) Priority (EDMA_CPR17) Priority (EDMA_CPR18) Priority (EDMA_CPR19)
eDMA Channel 28
eDMA Channel 29
eDMA Channel 30
eDMA Channel 31
Priority (EDMA_CPR16) Priority (EDMA_CPR17) Priority (EDMA_CPR18) Priority (EDMA_CPR19)
TCD00–TCD15
TCD16–TCD31
Reserved
24.3.2 Register Descriptions
This section lists the eDMA registers in address order and describes the registers and their bit fields.
Reading reserved bits in a register returns the value of zero. Writes to reserved bits in a register are ignored.
Reading or writing to a reserved memory location generates a bus error.
Many of the control registers have a bit width that matches the number of channels implemented in the
module, or 32 bits in size.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
24-7