PXN20RM Datasheet, PDF (114/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Resets
4.2.1 Reset (RESET)
This pin provides the system reset. It is an open-drain, active-low bidirectional pin. It acts as an input to
initialize the MCU to a known start-up state, and an output when an internal MCU function causes a reset.
Externally asserting the RESET pin resets the chip asynchronously. The chip remains in reset as long as
the external RESET pin is asserted. Any internal reset event asserts the RESET pin for as long as the reset
event is active. When the internal reset sources are negated, the RESET pin is asserted by the reset
controller for 1000 clocks (16 clocks if CRP_RECPRTR[FASTREC] = 1). Then the reset controller stops
asserting the RESET pin. After another predefined time, the RESET pin is sampled, and if still asserted
then an external reset request is assumed. When the RESET pin is sampled high (the pin is no longer being
driven low by the PXN20 reset logic or by external logic that might be requesting reset), the BOOTCFG
reset configuration pin (pin PK9) is sampled and the internal reset to the chip negates.
On assertion, the SIU_RSR[ERS] flag is set.
4.2.2 Boot Configuration (BOOTCFG)
The BOOTCFG pin (pin name PK9 in package diagrams and signal lists) is used to determine the boot
mode initiated by the BAM program. The pin state during reset is latched in the SIU_RSR[BOOTCFG]
field. The BAM program uses the BOOTCFG field to determine whether initiate internal flash boot mode
or a CAN or SCI “serial” boot.
Refer to 8.3.2.2, Reset Status Register (SIU_RSR), for more information.
NOTE
The reset controller latches the state of the BOOTCFG pin into the
SIU_RSR register 4 clock cycles prior to the negation of RESET.
4.3 Functional Description
4.3.1 Z6, Z0 Cores Reset Vectors
The reset vectors for the Z6 and Z0 cores in the PXN20 MCU are controlled via the Z6VEC and Z0VEC
registers in the Clock, Reset, and Power control (CRP) module. The power-on reset values for the Z6VEC
and Z0VEC registers point to the first instruction the BAM program.
The Z0 core is disabled after the POR and Z6 is active. Thus, following the POR, the Z6 core starts to
execute the BAM code. See Chapter 9, Boot Assist Module (BAM), for more details about the boot
process.
4.3.2 Reset Sources
4.3.2.1 Power-on Reset (POR)
The internal Power On Reset (POR) monitors the main supply input voltage (V_DDA) and shall not release
the internal reset line until V_DDA is above the de-assertion threshold. On assertion, the SIU_RSR[PORS]
flag is set.
PXN20 Microcontroller Reference Manual, Rev. 1
4-2
Freescale Semiconductor