PXN20RM Datasheet, PDF (968/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Deserial – Serial Peripheral Interface (DSPI)
PASC
0b01
Table 30-28. After SCK Delay Computation Example
Prescaler
Value
3
ASC
0b0100
Scaler
Value
32
Fsys
100 MHz
After SCK Delay
0.96 us
30.4.7.4 Delay after Transfer (t_DT)
The delay after transfer is the length of time between negation of the PCS signal for a frame and the
assertion of the PCS signal for the next frame. See Figure 30-29 for an illustration of the delay after
transfer. The PDT and DT fields in the DSPI_CTARn registers select the delay after transfer. The
following formula expresses the PDT/DT/delay after transfer relationship:
t_DT =
1
f_SYS ^{ PDT  DT}
Eqn. 30-7
Table 30-29 shows an example of the computed delay after transfer.
Table 30-29. Delay after Transfer Computation Example
PDT
0b01
Prescaler
Value
3
DT
0b1110
Scaler
Value
32768
f_SYS
Delay after Transfer
100 MHz
0.98 ms
When in non-continuous clock mode the T_DT delay is configurable as outlined in the DSPI_CTARn
registers. When in continuous clock mode and TSB is not enabled the delay is fixed at 1 SCK period. When
in TSB and continuous mode, the delay is programmed as outlined in the DSPI_CTARn registers. In event
that the delay does not coincide with an SCK period in duration, the delay is extended to the next SCK
active edge. Table 30-30 shows an example of how to compute the delay after Transfer with the clock
period of SCK defined as T_SCK. The values calculated assume 1 TSCK period = 4 ipg_clk.
30-42
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor