PXN20RM Datasheet, PDF (230/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

System Integration Unit (SIU)
8.3.2.27 Parallel GPIO Pin Data Output Register 0 (SIU_PGPDO0)
The SIU_PGPDO0 register contains the parallel GPIO pin data output for PB[0:15].
Reads and writes to this register are coherent with the registers SIU_GPDO16_19, SIU_GPDO20_23,
SIU_GPDO24_27, and SIU_GPDO28_31.
NOTE
On the PXN20, the port A pins are general-purpose inputs only. Therefore,
there are no parallel GPIO pin data output register bits for port A.
Offset: SIU_BASE + 0xC00
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
PB0:PB15
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 8-35. Parallel GPIO Pin Data Output Register 0 (SIU_PGPDO0)
8.3.2.28 Parallel GPIO Pin Data Output Register 1 (SIU_PGPDO1)
The SIU_PGPDO1 register contains the parallel GPIO pin data output for PC[0:15] and PD[0:15].
Reads and writes to this register are coherent with the registers SIU_GPDO32_35, SIU_GPDO36_39,
SIU_GPDO40_43, SIU_GPDO44_47, SIU_GPDO48_51, SIU_GPDO52_55, SIU_GPDO56_59, and
SIU_GPDO60_63.
Offset: SIU_BASE + 0x0C04
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
PC0:PC15
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
PD0:PD15
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 8-36. Parallel GPIO Pin Data Output Register 1 (SIU_PGPDO1)
8-48
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor