SH7727 Datasheet, PDF (999/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 31 User-Debugging Interface (H-UDI)
31.4.3 H-UDI Reset
An H-UDI reset is executed by setting an H-UDI reset assert command in SDIR. An H-UDI reset
is of the same kind as a power-on reset. An H-UDI reset is released by inputting an H-UDI reset
negate command.
SDIR
H-UDI reset assert
H-UDI reset negate
Chip internal
reset
CPU state
Branch to H'A0000000
Figure 31.3 H-UDI Reset
31.4.4 H-UDI Interrupt
The H-UDI interrupt function generates an interrupt by setting a command from the H-UDI in the
SDIR. An H-UDI interrupt is a general exception/interrupt operation, resulting in a branch to an
address based on the VBR value plus offset, and return by the RTE instruction. This interrupt
request has a fixed priority level of 15.
H-UDI interrupts are not accepted in sleep mode or standby mode.
31.4.5 Bypass
Setting the command from H-UDI to SDIR allows to set the H-UDI pins to the bypass mode that
conforms with the JTAG standard.
31.4.6 Using H-UDI to Recover from Sleep Mode
It is possible to recover from sleep mode by setting a command (0001) from the H-UDI in SDIR.
Rev. 5.00 Dec 12, 2005 page 927 of 1034
REJ09B0254-0500